coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio_early.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <gpio.h>
4 #include "include/gpio.h"
5 
6 /* Early pad configuration */
7 static const struct pad_config early_gpio_table[] = {
8  // GPIO (ISH_GP2) = DGPU_PRESENT
9  PAD_CFG_GPI_TRIG_OWN(GPP_A20, NONE, DEEP, OFF, ACPI),
10  // GPIO (VRALERT#) <= DGPU_PWROK
11  PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, DEEP, OFF, ACPI),
12  // GPIO (CPU_GP3) => DGPU_HOLD_RST#
13  PAD_CFG_GPO(GPP_B4, 1, DEEP),
14  // GPIO (GSPI1_MISO) => DGPU_PWR_EN#
15  PAD_CFG_TERM_GPO(GPP_B21, 1, DN_20K, DEEP),
16  // UART2_RXD = LPSS_UART2_RXD
17  PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
18  // UART2_TXD = LPSS_UART2_TXD
19  PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
20  // SATALED# = SATA_LED#
21  PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
22 };
23 
25 {
27 }
void mainboard_config_stage_gpios(void)
Definition: gpio_early.c:24
static const struct pad_config early_gpio_table[]
Definition: gpio_early.c:7
#define GPP_B2
Definition: gpio_soc_defs.h:55
#define GPP_E8
#define GPP_C20
#define GPP_A20
#define GPP_C21
#define GPP_B21
Definition: gpio_soc_defs.h:74
#define GPP_B4
Definition: gpio_soc_defs.h:57
#define ARRAY_SIZE(a)
Definition: helpers.h:12
void gpio_configure_pads(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
program a particular set of GPIO
Definition: gpio.c:307
#define PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, own)
Definition: gpio_defs.h:311
#define PAD_CFG_TERM_GPO(pad, val, pull, rst)
Definition: gpio_defs.h:262
#define PAD_CFG_NF(pad, pull, rst, func)
Definition: gpio_defs.h:197
#define PAD_CFG_GPO(pad, val, rst)
Definition: gpio_defs.h:247