coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
nvs.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _BAYTRAIL_NVS_H_
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#define _BAYTRAIL_NVS_H_
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#include <
stdint.h
>
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struct
__packed
global_nvs
{
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/* Miscellaneous */
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u16
unused_was_osys
;
/* 0x00 - Operating System */
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u8
smif
;
/* 0x02 - SMI function call ("TRAP") */
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u8
unused_was_prm0
;
/* 0x03 - SMI function call parameter */
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u8
unused_was_prm1
;
/* 0x04 - SMI function call parameter */
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u8
scif
;
/* 0x05 - SCI function call (via _L00) */
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u8
unused_was_prm2
;
/* 0x06 - SCI function call parameter */
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u8
unused_was_prm3
;
/* 0x07 - SCI function call parameter */
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u8
unused_was_lckf
;
/* 0x08 - Global Lock function for EC */
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u8
unused_was_prm4
;
/* 0x09 - Lock function parameter */
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u8
unused_was_prm5
;
/* 0x0a - Lock function parameter */
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u32
p80d
;
/* 0x0b - Debug port (IO 0x80) value */
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u8
lids
;
/* 0x0f - LID state (open = 1) */
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u8
unused_was_pwrs
;
/* 0x10 - Power state (AC = 1) */
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u8
unused_was_pcnt
;
/* 0x11 - Processor Count */
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u8
tpmp
;
/* 0x12 - TPM Present and Enabled */
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u8
tlvl
;
/* 0x13 - Throttle Level */
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u8
ppcm
;
/* 0x14 - Maximum P-state usable by OS */
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u32
pm1i
;
/* 0x15 - System Wake Source - PM1 Index */
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u32
gpei
;
/* 0x19 - GPE Wake Source */
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u8
rsvd1
[3];
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/* Device Config */
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u8
s5u0
;
/* 0x20 - Enable USB0 in S5 */
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u8
s5u1
;
/* 0x21 - Enable USB1 in S5 */
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u8
s3u0
;
/* 0x22 - Enable USB0 in S3 */
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u8
s3u1
;
/* 0x23 - Enable USB1 in S3 */
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u8
tact
;
/* 0x24 - Thermal Active trip point */
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u8
tpsv
;
/* 0x25 - Thermal Passive trip point */
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u8
tcrt
;
/* 0x26 - Thermal Critical trip point */
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u8
dpte
;
/* 0x27 - Enable DPTF */
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u8
rsvd2[8];
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/* Base Addresses */
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u32
obsolete_cmem
;
/* 0x30 - CBMEM TOC */
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u32
tolm
;
/* 0x34 - Top of Low Memory */
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u32
cbmc
;
/* 0x38 - coreboot memconsole */
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};
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#endif
/* _BAYTRAIL_NVS_H_ */
stdint.h
u32
uint32_t u32
Definition:
stdint.h:51
u16
uint16_t u16
Definition:
stdint.h:48
u8
uint8_t u8
Definition:
stdint.h:45
__packed
Definition:
x86.c:23
__packed::rsvd1
u32 rsvd1
Definition:
me.h:413
global_nvs
Definition:
nvs.h:14
global_nvs::unused_was_prm0
u8 unused_was_prm0
Definition:
nvs.h:12
global_nvs::lids
u8 lids
Definition:
nvs.h:21
global_nvs::tcrt
u8 tcrt
Definition:
nvs.h:38
global_nvs::unused_was_prm5
u8 unused_was_prm5
Definition:
nvs.h:19
global_nvs::gpei
u32 gpei
Definition:
nvs.h:28
global_nvs::s5u1
u8 s5u1
Definition:
nvs.h:33
global_nvs::p80d
u32 p80d
Definition:
nvs.h:20
global_nvs::s3u0
u8 s3u0
Definition:
nvs.h:34
global_nvs::tolm
u32 tolm
Definition:
nvs.h:44
global_nvs::unused_was_prm1
u8 unused_was_prm1
Definition:
nvs.h:13
global_nvs::obsolete_cmem
u32 obsolete_cmem
Definition:
nvs.h:43
global_nvs::s3u1
u8 s3u1
Definition:
nvs.h:35
global_nvs::unused_was_pcnt
u8 unused_was_pcnt
Definition:
nvs.h:23
global_nvs::s5u0
u8 s5u0
Definition:
nvs.h:32
global_nvs::tpmp
u8 tpmp
Definition:
nvs.h:24
global_nvs::unused_was_lckf
u8 unused_was_lckf
Definition:
nvs.h:17
global_nvs::ppcm
u8 ppcm
Definition:
nvs.h:26
global_nvs::dpte
u8 dpte
Definition:
nvs.h:39
global_nvs::tpsv
u8 tpsv
Definition:
nvs.h:37
global_nvs::scif
u8 scif
Definition:
nvs.h:14
global_nvs::unused_was_prm2
u8 unused_was_prm2
Definition:
nvs.h:15
global_nvs::pm1i
u32 pm1i
Definition:
nvs.h:27
global_nvs::unused_was_pwrs
u8 unused_was_pwrs
Definition:
nvs.h:22
global_nvs::tlvl
u8 tlvl
Definition:
nvs.h:25
global_nvs::cbmc
u32 cbmc
Definition:
nvs.h:45
global_nvs::unused_was_osys
u16 unused_was_osys
Definition:
nvs.h:10
global_nvs::unused_was_prm3
u8 unused_was_prm3
Definition:
nvs.h:16
global_nvs::unused_was_prm4
u8 unused_was_prm4
Definition:
nvs.h:18
global_nvs::tact
u8 tact
Definition:
nvs.h:36
global_nvs::smif
u8 smif
Definition:
nvs.h:11
src
soc
intel
baytrail
include
soc
nvs.h
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