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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Macros | |
| #define | I2C_MASTER_DEV_COUNT 4 |
| #define | I2C_MASTER_START_INDEX 2 |
| #define | I2C_PERIPHERAL_DEV_COUNT 1 |
| #define | I2C_CTRLR_COUNT (I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT) |
| #define | FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) |
| #define | ACPI_IO_BASE 0x400 |
| #define | ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) /* 4 bytes */ |
| #define | ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) /* 2 bytes */ |
| #define | ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */ |
| #define | ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) /* 2 bytes */ |
| #define | ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) /* 4 bytes */ |
| #define | ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10) |
| #define | ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) /* 8 bytes */ |
| #define | ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */ |
| #define | ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */ |
| #define | SMB_BASE_ADDR 0xb00 |
| #define | PM2_INDEX 0xcd0 |
| #define | PM2_DATA 0xcd1 |
| #define | BIOSRAM_INDEX 0xcd4 |
| #define | BIOSRAM_DATA 0xcd5 |
| #define | AB_INDX 0xcd8 |
| #define | AB_DATA (AB_INDX+4) |
| #define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10) |
| #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) /* 8 bytes */ |
| #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */ |
| #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */ |
| #define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) /* 2 bytes */ |
| #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */ |
| #define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) /* 2 bytes */ |
| #define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) /* 4 bytes */ |
| #define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) /* 4 bytes */ |
| #define I2C_CTRLR_COUNT (I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT) |
1.9.1