coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
BiosCallOuts.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <AGESA.h>
4 #include <amdlib.h>
5 #include <amdblocks/acpimmio.h>
7 #include <SB800.h>
8 
9 static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
10 static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr);
11 
13 {
14  {AGESA_DO_RESET, agesa_Reset },
15  {AGESA_READ_SPD, agesa_ReadSpd },
16  {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
17  {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
18  {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset },
19  {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit },
20  {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess },
21  {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
22  {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
23 };
25 
26 /* Call the host environment interface to provide a user hook opportunity. */
27 static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
28 {
29  // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage.
30  // Make sure the right speed settings are selected.
31  ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5;
32  return AGESA_SUCCESS;
33 }
34 
35 /* PCIE slot reset control */
36 static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
37 {
38  AGESA_STATUS Status;
39  PCIe_SLOT_RESET_INFO *ResetInfo;
40 
41  UINT32 GpioMmioAddr;
42  UINT8 Data8;
43 
44  ResetInfo = ConfigPtr;
45  Status = AGESA_UNSUPPORTED;
46  GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
47  switch (ResetInfo->ResetId)
48  {
49  case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot
50  switch (ResetInfo->ResetControl) {
51  case AssertSlotReset:
52  Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50);
53  Data8 &= ~(UINT8)BIT6;
54  Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8);
55  Status = AGESA_SUCCESS;
56  break;
57  case DeassertSlotReset:
58  Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50);
59  Data8 |= BIT6;
60  Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8);
61  Status = AGESA_SUCCESS;
62  break;
63  }
64  break;
65  }
66  return Status;
67 }
#define AGESA_SUCCESS
Definition: Amd.h:38
unsigned int AGESA_STATUS
Definition: Amd.h:36
#define AGESA_UNSUPPORTED
Definition: Amd.h:41
#define BIT6
Definition: Ioh.h:13
uint8_t *MAYBE_CONST acpimmio_gpio_100
#define ARRAY_SIZE(a)
Definition: helpers.h:12
AGESA_STATUS agesa_RunFuncOnAp(UINT32 Func, UINTN Data, VOID *ConfigPtr)
Definition: def_callouts.c:102
AGESA_STATUS agesa_NoopUnsupported(UINT32 Func, UINTN Data, VOID *ConfigPtr)
Definition: def_callouts.c:48
AGESA_STATUS agesa_NoopSuccess(UINT32 Func, UINTN Data, VOID *ConfigPtr)
Definition: def_callouts.c:53
AGESA_STATUS agesa_Reset(UINT32 Func, UINTN Data, VOID *ConfigPtr)
Definition: def_callouts.c:66
const int BiosCalloutsLen
Definition: BiosCallOuts.c:25
const BIOS_CALLOUT_STRUCT BiosCallouts[]
Definition: BiosCallOuts.c:13
static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data, VOID *ConfigPtr)
Definition: BiosCallOuts.c:27
static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr)
Definition: BiosCallOuts.c:36
AGESA_STATUS agesa_ReadSpd(uint32_t Func, uintptr_t Data, void *ConfigPtr)
Definition: BiosCallOuts.c:81
unsigned long uintptr_t
Definition: stdint.h:21