coreboot
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mcucfg.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 /*
4  * This file is created based on MT8186 Functional Specification
5  * Chapter number: 4.1
6  */
7 
8 #ifndef SOC_MEDIATEK_MT8186_MCUCFG_H
9 #define SOC_MEDIATEK_MT8186_MCUCFG_H
10 
11 #include <soc/addressmap.h>
12 #include <types.h>
13 
14 struct mt8186_mcucfg_regs {
15  u32 reserved1[2];
16  u32 mbista_mcsi_sf1_con;
17  u32 mbista_mcsi_sf1_result;
18  u32 mbista_mcsi_sf2_con;
19  u32 mbista_mcsi_sf2_result;
20  u32 mbista_etb_con;
21  u32 mbista_etb_result;
22  u32 mbista_rstb;
23  u32 mbista_all_result;
24  u32 reserved2[2];
25  u32 mbist_trigger_mux_ctl;
26  u32 reserved3[3];
27  u32 dfd_ctrl;
28  u32 dfd_cnt_l;
29  u32 dfd_cnt_h;
30  u32 reserved4[5];
31  u32 mp_top_dbg_mon_sel;
32  u32 mp_top_dbg_mon;
33  u32 mp0_dbg_mon_sel;
34  u32 mp0_dbg_mon;
35  u32 reserved5[8];
36  u32 l2_parity_clr;
37  u32 l2_parity_info1_cpu0;
38  u32 l2_parity_info2_cpu0;
39  u32 l2_parity_info1_cpu1;
40  u32 l2_parity_info2_cpu1;
41  u32 l2_parity_info1_cpu2;
42  u32 l2_parity_info2_cpu2;
43  u32 l2_parity_info1_cpu3;
44  u32 l2_parity_info2_cpu3;
45  u32 l2_parity_info1_cpu4;
46  u32 l2_parity_info2_cpu4;
47  u32 l2_parity_info1_cpu5;
48  u32 l2_parity_info2_cpu5;
49  u32 l2_parity_info1_cpu6;
50  u32 l2_parity_info2_cpu6;
51  u32 l2_parity_info1_cpu7;
52  u32 l2_parity_info2_cpu7;
53  u32 reserved6[10];
54  u32 apmcu2emi_early_cke_ctl;
55  u32 cci_tra_cfg0;
56  u32 reserved7[4];
57  u32 cci_tra_cfg5;
58  u32 cci_tra_cfg6;
59  u32 cci_tra_cfg7;
60  u32 cci_tra_cfg8;
61  u32 cci_tra_cfg9;
62  u32 cci_tra_cfg10;
63  u32 cci_tra_cfg11;
64  u32 cci_tra_cfg12;
65  u32 reserved8[51];
66  u32 cci_m0_tra;
67  u32 cci_m1_tra;
68  u32 cci_m2_tra;
69  u32 reserved9[5];
70  u32 cci_s1_tra;
71  u32 cci_s2_tra;
72  u32 cci_s3_tra;
73  u32 cci_s4_tra;
74  u32 reserved10[4];
75  u32 cci_m0_tra_latch;
76  u32 cci_m1_tra_latch;
77  u32 cci_m2_tra_latch;
78  u32 reserved11[5];
79  u32 cci_s1_tra_latch;
80  u32 cci_s2_tra_latch;
81  u32 cci_s3_tra_latch;
82  u32 cci_s4_tra_latch;
83  u32 reserved12[20];
84  u32 cci_m0_if;
85  u32 cci_m1_if;
86  u32 cci_m2_if;
87  u32 reserved13[5];
88  u32 cci_s1_if;
89  u32 cci_s2_if;
90  u32 cci_s3_if;
91  u32 cci_s4_if;
92  u32 reserved14[4];
93  u32 cci_top_if;
94  u32 reserved15[7];
95  u32 cci_m0_if_latch;
96  u32 cci_m1_if_latch;
97  u32 cci_m2_if_latch;
98  u32 reserved16[5];
99  u32 cci_s1_if_latch;
100  u32 cci_s2_if_latch;
101  u32 cci_s3_if_latch;
102  u32 cci_s4_if_latch;
103  u32 reserved17[4];
104  u32 cci_top_if_latch;
105  u32 reserved18[39];
106  u32 l3c_share_status0;
107  u32 l3c_share_status1;
108  u32 l3c_share_status2;
109  u32 reserved19[1];
110  u32 mp0_cpu0_dc_age;
111  u32 mp0_cpu1_dc_age;
112  u32 mp0_cpu2_dc_age;
113  u32 mp0_cpu3_dc_age;
114  u32 mp0_cpu4_dc_age;
115  u32 mp0_cpu5_dc_age;
116  u32 mp0_cpu6_dc_age;
117  u32 mp0_cpu7_dc_age;
118  u32 reserved20[52];
119  u32 mp0_cpu0_nonwfx_ctrl;
120  u32 mp0_cpu0_nonwfx_cnt;
121  u32 mp0_cpu1_nonwfx_ctrl;
122  u32 mp0_cpu1_nonwfx_cnt;
123  u32 mp0_cpu2_nonwfx_ctrl;
124  u32 mp0_cpu2_nonwfx_cnt;
125  u32 mp0_cpu3_nonwfx_ctrl;
126  u32 mp0_cpu3_nonwfx_cnt;
127  u32 mp0_cpu4_nonwfx_ctrl;
128  u32 mp0_cpu4_nonwfx_cnt;
129  u32 mp0_cpu5_nonwfx_ctrl;
130  u32 mp0_cpu5_nonwfx_cnt;
131  u32 mp0_cpu6_nonwfx_ctrl;
132  u32 mp0_cpu6_nonwfx_cnt;
133  u32 mp0_cpu7_nonwfx_ctrl;
134  u32 mp0_cpu7_nonwfx_cnt;
135  u32 reserved21[48];
136  u32 mp0_ses_apb_trig;
137  u32 reserved22[3];
138  u32 wfx_ret_met_dbc_sel;
139  u32 reserved23[3];
140  u32 adb_bist_cfg1;
141  u32 adb_bist_cfg2_md;
142  u32 adb_bist_cfg3_go;
143  u32 adb_bist_done;
144  u32 adb_bist_pass;
145  u32 reserved24[1667];
146  u32 dfd_internal_ctl;
147  u32 dfd_internal_counter;
148  u32 dfd_internal_pwr_on;
149  u32 dfd_internal_chain_legth_0;
150  u32 dfd_internal_shift_clk_ratio;
151  u32 dfd_internal_counter_return;
152  u32 dfd_internal_sram_access;
153  u32 dfd_internal_chain_length_1;
154  u32 dfd_internal_chain_length_2;
155  u32 dfd_internal_chain_length_3;
156  u32 dfd_internal_test_so_0;
157  u32 dfd_internal_test_so_1;
158  u32 dfd_internal_num_of_test_so_gp;
159  u32 dfd_internal_test_so_over_64;
160  u32 dfd_internal_mask_out;
161  u32 dfd_internal_sw_ns_trigger;
162  u32 dfd_internal_mcsi;
163  u32 dfd_internal_mcsi_sel_status;
164  u32 dfd_v30_ctl;
165  u32 dfd_v30_base_addr;
166  u32 dfd_power_ctl;
167  u32 dfd_reset_on;
168  u32 dfd_test_si_0;
169  u32 dfd_test_si_1;
170  u32 dfd_status_clean;
171  u32 dfd_status_return;
172  u32 reserved25[21];
173  u32 dfd_hw_trigger_mask;
174  u32 reserved26[64];
175  u32 mcusys_par_wrap_dbg_mon_sel;
176  u32 mcusys_par_wrap_dbg_mon;
177  u32 mcusys_pinmux;
178  u32 reserved27[1];
179  u32 l3c_share_cfg0;
180  u32 l3c_share_cfg1;
181  u32 l3c_share_cfg2;
182  u32 reserved28[1];
183  u32 udi_cfg0;
184  u32 udi_cfg1;
185  u32 reserved29[2];
186  u32 mcusys_core_status;
187  u32 reserved30[11];
188  u32 mcusys_base;
189  u32 l3c_sram_base;
190  u32 gic_periph_base;
191  u32 cci_periph_base;
192  u32 cci_periph_infra_base;
193  u32 dfd_sram_base;
194  u32 l3c_mm_sram_base;
195  u32 reserved31[9];
196  u32 cpu_plldiv_cfg0;
197  u32 cpu_plldiv_cfg1;
198  u32 cpu_plldiv_cfg2;
199  u32 reserved32[13];
200  u32 bus_plldiv_cfg;
201  u32 reserved33[3];
202  u32 plldiv_ctl0;
203  u32 reserved34[3];
204  u32 mcsi_ram_delsel0;
205  u32 mcsi_ram_delsel1;
206  u32 reserved35[6];
207  u32 etb_ram_delsel0;
208  u32 reserved36[23];
209  u32 etb_cfg0;
210  u32 reserved37[31];
211  u32 cci_rgu;
212  u32 reserved38[3];
213  u32 mcsi_cfg0;
214  u32 mcsi_cfg1;
215  u32 mcsi_cfg2;
216  u32 mcsi_cfg3;
217  u32 mcsi_cfg4;
218  u32 reserved39[7];
219  u32 mcsic_dcm0;
220  u32 mcsic_dcm1;
221  u32 reserved40[46];
222  u32 mp_adb_dcm_cfg0;
223  u32 reserved41[1];
224  u32 mp_adb_dcm_cfg2;
225  u32 reserved42[1];
226  u32 mp_adb_dcm_cfg4;
227  u32 reserved43[1];
228  u32 mp_misc_dcm_cfg0;
229  u32 reserved44[9];
230  u32 etb_ck_ctl;
231  u32 reserved45[15];
232  u32 dcc_cpu_con0;
233  u32 dcc_cpu_con1;
234  u32 dcc_cpu_con2;
235  u32 reserved46[5];
236  u32 dcc_bus_con0;
237  u32 reserved47[7];
238  u32 mcusys_dcm_cfg0;
239  u32 reserved48[15];
240  u32 sec_pol_ctl_en0;
241  u32 sec_pol_ctl_en1;
242  u32 sec_pol_ctl_en2;
243  u32 sec_pol_ctl_en3;
244  u32 sec_pol_ctl_en4;
245  u32 sec_pol_ctl_en5;
246  u32 sec_pol_ctl_en6;
247  u32 sec_pol_ctl_en7;
248  u32 sec_pol_ctl_en8;
249  u32 sec_pol_ctl_en9;
250  u32 sec_pol_ctl_en10;
251  u32 sec_pol_ctl_en11;
252  u32 sec_pol_ctl_en12;
253  u32 sec_pol_ctl_en13;
254  u32 sec_pol_ctl_en14;
255  u32 sec_pol_ctl_en15;
256  u32 sec_pol_ctl_en16;
257  u32 sec_pol_ctl_en17;
258  u32 sec_pol_ctl_en18;
259  u32 sec_pol_ctl_en19;
260  u32 int_pol_ctl0;
261  u32 int_pol_ctl1;
262  u32 int_pol_ctl2;
263  u32 int_pol_ctl3;
264  u32 int_pol_ctl4;
265  u32 int_pol_ctl5;
266  u32 int_pol_ctl6;
267  u32 int_pol_ctl7;
268  u32 int_pol_ctl8;
269  u32 int_pol_ctl9;
270  u32 int_pol_ctl10;
271  u32 int_pol_ctl11;
272  u32 int_pol_ctl12;
273  u32 int_pol_ctl13;
274  u32 int_pol_ctl14;
275  u32 int_pol_ctl15;
276  u32 int_pol_ctl16;
277  u32 int_pol_ctl17;
278  u32 int_pol_ctl18;
279  u32 int_pol_ctl19;
280  u32 int_msk_ctl0;
281  u32 int_msk_ctl1;
282  u32 int_msk_ctl2;
283  u32 int_msk_ctl3;
284  u32 int_msk_ctl4;
285  u32 int_msk_ctl5;
286  u32 int_msk_ctl6;
287  u32 int_msk_ctl7;
288  u32 int_msk_ctl8;
289  u32 int_msk_ctl9;
290  u32 int_msk_ctl10;
291  u32 int_msk_ctl11;
292  u32 int_msk_ctl12;
293  u32 int_msk_ctl13;
294  u32 int_msk_ctl14;
295  u32 int_msk_ctl15;
296  u32 int_msk_ctl16;
297  u32 int_msk_ctl17;
298  u32 int_msk_ctl18;
299  u32 int_msk_ctl19;
300  u32 reserved49[1];
301  u32 int_msk_ctl_all;
302  u32 int_cfg_indirect_access;
303  u32 int_cfg_direct_access_en;
304  u32 fcm_spmc_sw_cfg1;
305  u32 fcm_spmc_sw_cfg2;
306  u32 fcm_spmc_wait_cfg;
307  u32 fcm_spmc_sw_pchannel;
308  u32 fcm_spmc_pwr_status;
309  u32 fcm_spmc_off_thres;
310  u32 fcm_spmc_wdt_latch_info;
311  u32 reserved50[9];
312  u32 mcusys_spmc_sw_cfg;
313  u32 mcusys_spmc_wait_cfg;
314  u32 mcusys_spmc_pwr_status;
315  u32 reserved51[45];
316  u32 cpc_pllbuck_req_ctrl;
317  u32 mcusys_pwr_ctrl;
318  u32 cpusys_pwr_ctrl;
319  u32 sw_gic_wakeup_req;
320  u32 cpc_pllbuck_arb_weight;
321  u32 cpc_flow_ctrl_cfg;
322  u32 cpc_last_core_req;
323  u32 cpc_cpusys_last_core_resp;
324  u32 reserved52[1];
325  u32 cpc_mcusys_last_core_resp;
326  u32 cpc_pwr_on_mask;
327  u32 reserved53[5];
328  u32 cpc_spmc_pwr_status;
329  u32 cpc_core_cur_fsm;
330  u32 cpc_cpusys_mcusys_cur_fsm;
331  u32 cpc_wakeup_req;
332  u32 reserved54[3];
333  u32 cpc_turbo_ctrl;
334  u32 cpc_turbo_gp0_ctrl;
335  u32 cpc_turbo_gp1_ctrl;
336  u32 cpc_turbo_gp2_ctrl;
337  u32 cpc_turbo_pwr_on_mask;
338  u32 cpc_turbo_gp0_req;
339  u32 cpc_turbo_gp1_req;
340  u32 cpc_turbo_gp2_req;
341  u32 reserved55[1];
342  u32 cpc_turbo_gp0_resp;
343  u32 cpc_turbo_gp1_resp;
344  u32 cpc_turbo_gp2_resp;
345  u32 cpc_coh_block_thres;
346  u32 cpc_int_status;
347  u32 cpc_int_enable;
348  u32 pllbuck_group_func;
349  u32 cpc_dcm_enable;
350  u32 cpc_pllbuck_state;
351  u32 cpc_cpu_on_sw_hint;
352  u32 cpc_cpu_on_sw_hint_set;
353  u32 cpc_cpu_on_sw_hint_clear;
354  u32 reserved56[20];
355  u32 emi_wfifo;
356  u32 axi1to4_cfg;
357  u32 reserved57[1];
358  u32 emi_adb_edge_sel;
359  u32 reserved58[4];
360  u32 sclk_cfg_slow_down_ck;
361  u32 reserved59[27];
362  u32 mcusys_dbg_mon_sel;
363  u32 mcusys_dbg_mon;
364  u32 reserved60[58];
365  u32 gic_acao_ctl0;
366  u32 gic_acao_ctl1;
367  u32 gic_acao_ctl2;
368  u32 reserved61[29];
369  u32 spmc_dbg_setting;
370  u32 kernel_base_l;
371  u32 kernel_base_h;
372  u32 systime_base_l;
373  u32 systime_base_h;
374  u32 trace_data_selection;
375  u32 reserved62[2];
376  u32 trace_data_entry0_l;
377  u32 trace_data_entry0_h;
378  u32 trace_data_entry1_l;
379  u32 trace_data_entry1_h;
380  u32 trace_data_entry2_l;
381  u32 trace_data_entry2_h;
382  u32 trace_data_entry3_l;
383  u32 trace_data_entry3_h;
384  u32 cpu0_on_off_latency;
385  u32 cpu1_on_off_latency;
386  u32 cpu2_on_off_latency;
387  u32 cpu3_on_off_latency;
388  u32 cpu4_on_off_latency;
389  u32 cpu5_on_off_latency;
390  u32 cpu6_on_off_latency;
391  u32 cpu7_on_off_latency;
392  u32 cluster_off_latency;
393  u32 cluster_on_latency;
394  u32 mcusys_on_off_latency;
395  u32 reserved63[1];
396  u32 cluster_off_dormant_counter;
397  u32 cluster_off_dormant_counter_clear;
398  u32 reserved64[2];
399  u32 cpc_wdt_latch_info1;
400  u32 cpc_wdt_latch_info2;
401  u32 cpc_wdt_latch_info3;
402  u32 cpc_wdt_latch_info4;
403  u32 cpc_wdt_latch_info5;
404  u32 cpc_pmu_ctrl;
405  u32 cpc_pmu_cnt_clr;
406  u32 cpc_pmu_cnt0;
407  u32 reserved65[88];
408  u32 ildo_vproc2_en;
409  u32 reserved66[63];
410  u32 pikachu_event;
411  u32 pikachu_status;
412  u32 reserved67[126];
413  u32 cpu0_drcc_ao_config;
414  u32 reserved68[125];
415  u32 cpu0_resereved_reg;
416  u32 cpu0_resereved_reg_rd;
417  u32 cpu1_drcc_ao_config;
418  u32 reserved69[125];
419  u32 cpu1_resereved_reg;
420  u32 cpu1_resereved_reg_rd;
421  u32 cpu2_drcc_ao_config;
422  u32 reserved70[125];
423  u32 cpu2_resereved_reg;
424  u32 cpu2_resereved_reg_rd;
425  u32 cpu3_drcc_ao_config;
426  u32 reserved71[125];
427  u32 cpu3_resereved_reg;
428  u32 cpu3_resereved_reg_rd;
429  u32 cpu4_drcc_ao_config;
430  u32 reserved72[125];
431  u32 cpu4_resereved_reg;
432  u32 cpu4_resereved_reg_rd;
433  u32 cpu5_drcc_ao_config;
434  u32 reserved73[125];
435  u32 cpu5_resereved_reg;
436  u32 cpu5_resereved_reg_rd;
437  u32 cpu6_drcc_ao_config;
438  u32 reserved74[125];
439  u32 cpu6_resereved_reg;
440  u32 cpu6_resereved_reg_rd;
441  u32 cpu7_drcc_ao_config;
442  u32 reserved75[125];
443  u32 cpu7_resereved_reg;
444  u32 cpu7_resereved_reg_rd;
445  u32 reserved76[528];
446  u32 mp0_l3_data_ram_delsel;
447  u32 mp0_l3_tag_ram_delsel;
448  u32 mp0_l3_victim_ram_delsel;
449  u32 mp0_l3_scu_sf_ram_delsel;
450  u32 reserved77[12];
451  u32 mp0_dcm_cfg0;
452  u32 mp0_dcm_cfg1;
453  u32 mp0_dcm_cfg2;
454  u32 mp0_dcm_cfg3;
455  u32 mp0_dcm_cfg4;
456  u32 mp0_dcm_cfg5;
457  u32 mp0_dcm_cfg6;
458  u32 mp0_dcm_cfg7;
459  u32 mp0_dcm_cfg8;
460  u32 reserved78[7];
461  u32 mp0_l3_cache_parity1;
462  u32 mp0_l3_cache_parity2;
463  u32 mp0_l3_cache_parity3;
464  u32 reserved79[1];
465  u32 mp0_cluster_cfg0;
466  u32 reserved80[3];
467  u32 mp0_cluster_cfg4;
468  u32 mp0_cluster_cfg5;
469  u32 mp0_cluster_cfg6;
470  u32 mp0_cluster_cfg7;
471  u32 reserved81[4];
472  u32 mp0_cluster_cfg8;
473  u32 mp0_cluster_cfg9;
474  u32 mp0_cluster_cfg10;
475  u32 mp0_cluster_cfg11;
476  u32 mp0_cluster_cfg12;
477  u32 mp0_cluster_cfg13;
478  u32 mp0_cluster_cfg14;
479  u32 mp0_cluster_cfg15;
480  u32 mp0_cluster_cfg16;
481  u32 mp0_cluster_cfg17;
482  u32 mp0_cluster_cfg18;
483  u32 mp0_cluster_cfg19;
484  u32 mp0_cluster_cfg20;
485  u32 mp0_cluster_cfg21;
486  u32 mp0_cluster_cfg22;
487  u32 mp0_cluster_cfg23;
488  u32 reserved82[1];
489  u32 mp0_victim_rd_mask;
490  u32 reserved83[174];
491  u32 cpu_type0_spmc0_cfg;
492  u32 reserved84[7];
493  u32 cpu_type0_ram_delsel0_cfg;
494  u32 cpu_type0_ram_delsel1_cfg;
495  u32 cpu_type0_ram_delsel2_cfg;
496  u32 reserved85[53];
497  u32 cpu_type1_spmc0_cfg;
498  u32 reserved86[3];
499  u32 cpu_type1_mpmmen;
500  u32 reserved87[3];
501  u32 cpu_type1_ram_delsel0_cfg;
502  u32 cpu_type1_ram_delsel1_cfg;
503  u32 cpu_type1_ram_delsel2_cfg;
504  u32 reserved88[53];
505  u32 plldiv_turbo;
506  u32 plldiv_percore_dfs_1;
507  u32 plldiv_percore_dfs_2;
508  u32 plldiv_imax_cg;
509  u32 plldiv_imax_int;
510  u32 plldiv_imax_detector;
511  u32 plldiv_little_reserved;
512  u32 plldiv_big_reserved;
513  u32 plldiv_bus_reserved;
514  u32 reserved89[3183];
515  u32 mcusys_reserved_reg0;
516  u32 mcusys_reserved_reg1;
517  u32 mcusys_reserved_reg2;
518  u32 mcusys_reserved_reg3;
519  u32 mcusys_reserved_reg0_rd;
520  u32 mcusys_reserved_reg1_rd;
521  u32 mcusys_reserved_reg2_rd;
522  u32 mcusys_reserved_reg3_rd;
523 };
524 
525 check_member(mt8186_mcucfg_regs, mbista_mcsi_sf1_con, 0x8);
526 check_member(mt8186_mcucfg_regs, mbista_mcsi_sf1_result, 0xc);
527 check_member(mt8186_mcucfg_regs, mbista_mcsi_sf2_con, 0x10);
528 check_member(mt8186_mcucfg_regs, mbista_mcsi_sf2_result, 0x14);
529 check_member(mt8186_mcucfg_regs, mbista_etb_con, 0x18);
530 check_member(mt8186_mcucfg_regs, mbista_etb_result, 0x1c);
531 check_member(mt8186_mcucfg_regs, mbista_rstb, 0x20);
532 check_member(mt8186_mcucfg_regs, mbista_all_result, 0x24);
533 check_member(mt8186_mcucfg_regs, mbist_trigger_mux_ctl, 0x30);
534 check_member(mt8186_mcucfg_regs, dfd_ctrl, 0x40);
535 check_member(mt8186_mcucfg_regs, dfd_cnt_l, 0x44);
536 check_member(mt8186_mcucfg_regs, dfd_cnt_h, 0x48);
537 check_member(mt8186_mcucfg_regs, mp_top_dbg_mon_sel, 0x60);
538 check_member(mt8186_mcucfg_regs, mp_top_dbg_mon, 0x64);
539 check_member(mt8186_mcucfg_regs, mp0_dbg_mon_sel, 0x68);
540 check_member(mt8186_mcucfg_regs, mp0_dbg_mon, 0x6c);
541 check_member(mt8186_mcucfg_regs, l2_parity_clr, 0x90);
542 check_member(mt8186_mcucfg_regs, l2_parity_info1_cpu0, 0x94);
543 check_member(mt8186_mcucfg_regs, l2_parity_info2_cpu0, 0x98);
544 check_member(mt8186_mcucfg_regs, l2_parity_info1_cpu1, 0x9c);
545 check_member(mt8186_mcucfg_regs, l2_parity_info2_cpu1, 0xa0);
546 check_member(mt8186_mcucfg_regs, l2_parity_info1_cpu2, 0xa4);
547 check_member(mt8186_mcucfg_regs, l2_parity_info2_cpu2, 0xa8);
548 check_member(mt8186_mcucfg_regs, l2_parity_info1_cpu3, 0xac);
549 check_member(mt8186_mcucfg_regs, l2_parity_info2_cpu3, 0xb0);
550 check_member(mt8186_mcucfg_regs, l2_parity_info1_cpu4, 0xb4);
551 check_member(mt8186_mcucfg_regs, l2_parity_info2_cpu4, 0xb8);
552 check_member(mt8186_mcucfg_regs, l2_parity_info1_cpu5, 0xbc);
553 check_member(mt8186_mcucfg_regs, l2_parity_info2_cpu5, 0xc0);
554 check_member(mt8186_mcucfg_regs, l2_parity_info1_cpu6, 0xc4);
555 check_member(mt8186_mcucfg_regs, l2_parity_info2_cpu6, 0xc8);
556 check_member(mt8186_mcucfg_regs, l2_parity_info1_cpu7, 0xcc);
557 check_member(mt8186_mcucfg_regs, l2_parity_info2_cpu7, 0xd0);
558 check_member(mt8186_mcucfg_regs, apmcu2emi_early_cke_ctl, 0xfc);
559 check_member(mt8186_mcucfg_regs, cci_tra_cfg0, 0x100);
560 check_member(mt8186_mcucfg_regs, cci_tra_cfg5, 0x114);
561 check_member(mt8186_mcucfg_regs, cci_tra_cfg6, 0x118);
562 check_member(mt8186_mcucfg_regs, cci_tra_cfg7, 0x11c);
563 check_member(mt8186_mcucfg_regs, cci_tra_cfg8, 0x120);
564 check_member(mt8186_mcucfg_regs, cci_tra_cfg9, 0x124);
565 check_member(mt8186_mcucfg_regs, cci_tra_cfg10, 0x128);
566 check_member(mt8186_mcucfg_regs, cci_tra_cfg11, 0x12c);
567 check_member(mt8186_mcucfg_regs, cci_tra_cfg12, 0x130);
568 check_member(mt8186_mcucfg_regs, cci_m0_tra, 0x200);
569 check_member(mt8186_mcucfg_regs, cci_m1_tra, 0x204);
570 check_member(mt8186_mcucfg_regs, cci_m2_tra, 0x208);
571 check_member(mt8186_mcucfg_regs, cci_s1_tra, 0x220);
572 check_member(mt8186_mcucfg_regs, cci_s2_tra, 0x224);
573 check_member(mt8186_mcucfg_regs, cci_s3_tra, 0x228);
574 check_member(mt8186_mcucfg_regs, cci_s4_tra, 0x22c);
575 check_member(mt8186_mcucfg_regs, cci_m0_tra_latch, 0x240);
576 check_member(mt8186_mcucfg_regs, cci_m1_tra_latch, 0x244);
577 check_member(mt8186_mcucfg_regs, cci_m2_tra_latch, 0x248);
578 check_member(mt8186_mcucfg_regs, cci_s1_tra_latch, 0x260);
579 check_member(mt8186_mcucfg_regs, cci_s2_tra_latch, 0x264);
580 check_member(mt8186_mcucfg_regs, cci_s3_tra_latch, 0x268);
581 check_member(mt8186_mcucfg_regs, cci_s4_tra_latch, 0x26c);
582 check_member(mt8186_mcucfg_regs, cci_m0_if, 0x2c0);
583 check_member(mt8186_mcucfg_regs, cci_m1_if, 0x2c4);
584 check_member(mt8186_mcucfg_regs, cci_m2_if, 0x2c8);
585 check_member(mt8186_mcucfg_regs, cci_s1_if, 0x2e0);
586 check_member(mt8186_mcucfg_regs, cci_s2_if, 0x2e4);
587 check_member(mt8186_mcucfg_regs, cci_s3_if, 0x2e8);
588 check_member(mt8186_mcucfg_regs, cci_s4_if, 0x2ec);
589 check_member(mt8186_mcucfg_regs, cci_top_if, 0x300);
590 check_member(mt8186_mcucfg_regs, cci_m0_if_latch, 0x320);
591 check_member(mt8186_mcucfg_regs, cci_m1_if_latch, 0x324);
592 check_member(mt8186_mcucfg_regs, cci_m2_if_latch, 0x328);
593 check_member(mt8186_mcucfg_regs, cci_s1_if_latch, 0x340);
594 check_member(mt8186_mcucfg_regs, cci_s2_if_latch, 0x344);
595 check_member(mt8186_mcucfg_regs, cci_s3_if_latch, 0x348);
596 check_member(mt8186_mcucfg_regs, cci_s4_if_latch, 0x34c);
597 check_member(mt8186_mcucfg_regs, cci_top_if_latch, 0x360);
598 check_member(mt8186_mcucfg_regs, l3c_share_status0, 0x400);
599 check_member(mt8186_mcucfg_regs, l3c_share_status1, 0x404);
600 check_member(mt8186_mcucfg_regs, l3c_share_status2, 0x408);
601 check_member(mt8186_mcucfg_regs, mp0_cpu0_dc_age, 0x410);
602 check_member(mt8186_mcucfg_regs, mp0_cpu1_dc_age, 0x414);
603 check_member(mt8186_mcucfg_regs, mp0_cpu2_dc_age, 0x418);
604 check_member(mt8186_mcucfg_regs, mp0_cpu3_dc_age, 0x41c);
605 check_member(mt8186_mcucfg_regs, mp0_cpu4_dc_age, 0x420);
606 check_member(mt8186_mcucfg_regs, mp0_cpu5_dc_age, 0x424);
607 check_member(mt8186_mcucfg_regs, mp0_cpu6_dc_age, 0x428);
608 check_member(mt8186_mcucfg_regs, mp0_cpu7_dc_age, 0x42c);
609 check_member(mt8186_mcucfg_regs, mp0_cpu0_nonwfx_ctrl, 0x500);
610 check_member(mt8186_mcucfg_regs, mp0_cpu0_nonwfx_cnt, 0x504);
611 check_member(mt8186_mcucfg_regs, mp0_cpu1_nonwfx_ctrl, 0x508);
612 check_member(mt8186_mcucfg_regs, mp0_cpu1_nonwfx_cnt, 0x50c);
613 check_member(mt8186_mcucfg_regs, mp0_cpu2_nonwfx_ctrl, 0x510);
614 check_member(mt8186_mcucfg_regs, mp0_cpu2_nonwfx_cnt, 0x514);
615 check_member(mt8186_mcucfg_regs, mp0_cpu3_nonwfx_ctrl, 0x518);
616 check_member(mt8186_mcucfg_regs, mp0_cpu3_nonwfx_cnt, 0x51c);
617 check_member(mt8186_mcucfg_regs, mp0_cpu4_nonwfx_ctrl, 0x520);
618 check_member(mt8186_mcucfg_regs, mp0_cpu4_nonwfx_cnt, 0x524);
619 check_member(mt8186_mcucfg_regs, mp0_cpu5_nonwfx_ctrl, 0x528);
620 check_member(mt8186_mcucfg_regs, mp0_cpu5_nonwfx_cnt, 0x52c);
621 check_member(mt8186_mcucfg_regs, mp0_cpu6_nonwfx_ctrl, 0x530);
622 check_member(mt8186_mcucfg_regs, mp0_cpu6_nonwfx_cnt, 0x534);
623 check_member(mt8186_mcucfg_regs, mp0_cpu7_nonwfx_ctrl, 0x538);
624 check_member(mt8186_mcucfg_regs, mp0_cpu7_nonwfx_cnt, 0x53c);
625 check_member(mt8186_mcucfg_regs, mp0_ses_apb_trig, 0x600);
626 check_member(mt8186_mcucfg_regs, wfx_ret_met_dbc_sel, 0x610);
627 check_member(mt8186_mcucfg_regs, adb_bist_cfg1, 0x620);
628 check_member(mt8186_mcucfg_regs, adb_bist_cfg2_md, 0x624);
629 check_member(mt8186_mcucfg_regs, adb_bist_cfg3_go, 0x628);
630 check_member(mt8186_mcucfg_regs, adb_bist_done, 0x62c);
631 check_member(mt8186_mcucfg_regs, adb_bist_pass, 0x630);
632 check_member(mt8186_mcucfg_regs, dfd_internal_ctl, 0x2040);
633 check_member(mt8186_mcucfg_regs, dfd_internal_counter, 0x2044);
634 check_member(mt8186_mcucfg_regs, dfd_internal_pwr_on, 0x2048);
635 check_member(mt8186_mcucfg_regs, dfd_internal_chain_legth_0, 0x204c);
636 check_member(mt8186_mcucfg_regs, dfd_internal_shift_clk_ratio, 0x2050);
637 check_member(mt8186_mcucfg_regs, dfd_internal_counter_return, 0x2054);
638 check_member(mt8186_mcucfg_regs, dfd_internal_sram_access, 0x2058);
639 check_member(mt8186_mcucfg_regs, dfd_internal_chain_length_1, 0x205c);
640 check_member(mt8186_mcucfg_regs, dfd_internal_chain_length_2, 0x2060);
641 check_member(mt8186_mcucfg_regs, dfd_internal_chain_length_3, 0x2064);
642 check_member(mt8186_mcucfg_regs, dfd_internal_test_so_0, 0x2068);
643 check_member(mt8186_mcucfg_regs, dfd_internal_test_so_1, 0x206c);
644 check_member(mt8186_mcucfg_regs, dfd_internal_num_of_test_so_gp, 0x2070);
645 check_member(mt8186_mcucfg_regs, dfd_internal_test_so_over_64, 0x2074);
646 check_member(mt8186_mcucfg_regs, dfd_internal_mask_out, 0x2078);
647 check_member(mt8186_mcucfg_regs, dfd_internal_sw_ns_trigger, 0x207c);
648 check_member(mt8186_mcucfg_regs, dfd_internal_mcsi, 0x2080);
649 check_member(mt8186_mcucfg_regs, dfd_internal_mcsi_sel_status, 0x2084);
650 check_member(mt8186_mcucfg_regs, dfd_v30_ctl, 0x2088);
651 check_member(mt8186_mcucfg_regs, dfd_v30_base_addr, 0x208c);
652 check_member(mt8186_mcucfg_regs, dfd_power_ctl, 0x2090);
653 check_member(mt8186_mcucfg_regs, dfd_reset_on, 0x2094);
654 check_member(mt8186_mcucfg_regs, dfd_test_si_0, 0x2098);
655 check_member(mt8186_mcucfg_regs, dfd_test_si_1, 0x209c);
656 check_member(mt8186_mcucfg_regs, dfd_status_clean, 0x20a0);
657 check_member(mt8186_mcucfg_regs, dfd_status_return, 0x20a4);
658 check_member(mt8186_mcucfg_regs, dfd_hw_trigger_mask, 0x20fc);
659 check_member(mt8186_mcucfg_regs, mcusys_par_wrap_dbg_mon_sel, 0x2200);
660 check_member(mt8186_mcucfg_regs, mcusys_par_wrap_dbg_mon, 0x2204);
661 check_member(mt8186_mcucfg_regs, mcusys_pinmux, 0x2208);
662 check_member(mt8186_mcucfg_regs, l3c_share_cfg0, 0x2210);
663 check_member(mt8186_mcucfg_regs, l3c_share_cfg1, 0x2214);
664 check_member(mt8186_mcucfg_regs, l3c_share_cfg2, 0x2218);
665 check_member(mt8186_mcucfg_regs, udi_cfg0, 0x2220);
666 check_member(mt8186_mcucfg_regs, udi_cfg1, 0x2224);
667 check_member(mt8186_mcucfg_regs, mcusys_core_status, 0x2230);
668 check_member(mt8186_mcucfg_regs, mcusys_base, 0x2260);
669 check_member(mt8186_mcucfg_regs, l3c_sram_base, 0x2264);
670 check_member(mt8186_mcucfg_regs, gic_periph_base, 0x2268);
671 check_member(mt8186_mcucfg_regs, cci_periph_base, 0x226c);
672 check_member(mt8186_mcucfg_regs, cci_periph_infra_base, 0x2270);
673 check_member(mt8186_mcucfg_regs, dfd_sram_base, 0x2274);
674 check_member(mt8186_mcucfg_regs, l3c_mm_sram_base, 0x2278);
675 check_member(mt8186_mcucfg_regs, cpu_plldiv_cfg0, 0x22a0);
676 check_member(mt8186_mcucfg_regs, cpu_plldiv_cfg1, 0x22a4);
677 check_member(mt8186_mcucfg_regs, cpu_plldiv_cfg2, 0x22a8);
678 check_member(mt8186_mcucfg_regs, bus_plldiv_cfg, 0x22e0);
679 check_member(mt8186_mcucfg_regs, plldiv_ctl0, 0x22f0);
680 check_member(mt8186_mcucfg_regs, mcsi_ram_delsel0, 0x2300);
681 check_member(mt8186_mcucfg_regs, mcsi_ram_delsel1, 0x2304);
682 check_member(mt8186_mcucfg_regs, etb_ram_delsel0, 0x2320);
683 check_member(mt8186_mcucfg_regs, etb_cfg0, 0x2380);
684 check_member(mt8186_mcucfg_regs, cci_rgu, 0x2400);
685 check_member(mt8186_mcucfg_regs, mcsi_cfg0, 0x2410);
686 check_member(mt8186_mcucfg_regs, mcsi_cfg1, 0x2414);
687 check_member(mt8186_mcucfg_regs, mcsi_cfg2, 0x2418);
688 check_member(mt8186_mcucfg_regs, mcsi_cfg3, 0x241c);
689 check_member(mt8186_mcucfg_regs, mcsi_cfg4, 0x2420);
690 check_member(mt8186_mcucfg_regs, mcsic_dcm0, 0x2440);
691 check_member(mt8186_mcucfg_regs, mcsic_dcm1, 0x2444);
692 check_member(mt8186_mcucfg_regs, mp_adb_dcm_cfg0, 0x2500);
693 check_member(mt8186_mcucfg_regs, mp_adb_dcm_cfg2, 0x2508);
694 check_member(mt8186_mcucfg_regs, mp_adb_dcm_cfg4, 0x2510);
695 check_member(mt8186_mcucfg_regs, mp_misc_dcm_cfg0, 0x2518);
696 check_member(mt8186_mcucfg_regs, etb_ck_ctl, 0x2540);
697 check_member(mt8186_mcucfg_regs, dcc_cpu_con0, 0x2580);
698 check_member(mt8186_mcucfg_regs, dcc_cpu_con1, 0x2584);
699 check_member(mt8186_mcucfg_regs, dcc_cpu_con2, 0x2588);
700 check_member(mt8186_mcucfg_regs, dcc_bus_con0, 0x25a0);
701 check_member(mt8186_mcucfg_regs, mcusys_dcm_cfg0, 0x25c0);
702 check_member(mt8186_mcucfg_regs, sec_pol_ctl_en0, 0x2600);
703 check_member(mt8186_mcucfg_regs, sec_pol_ctl_en1, 0x2604);
704 check_member(mt8186_mcucfg_regs, sec_pol_ctl_en2, 0x2608);
705 check_member(mt8186_mcucfg_regs, sec_pol_ctl_en3, 0x260c);
706 check_member(mt8186_mcucfg_regs, sec_pol_ctl_en4, 0x2610);
707 check_member(mt8186_mcucfg_regs, sec_pol_ctl_en5, 0x2614);
708 check_member(mt8186_mcucfg_regs, sec_pol_ctl_en6, 0x2618);
709 check_member(mt8186_mcucfg_regs, sec_pol_ctl_en7, 0x261c);
710 check_member(mt8186_mcucfg_regs, sec_pol_ctl_en8, 0x2620);
711 check_member(mt8186_mcucfg_regs, sec_pol_ctl_en9, 0x2624);
712 check_member(mt8186_mcucfg_regs, sec_pol_ctl_en10, 0x2628);
713 check_member(mt8186_mcucfg_regs, sec_pol_ctl_en11, 0x262c);
714 check_member(mt8186_mcucfg_regs, sec_pol_ctl_en12, 0x2630);
715 check_member(mt8186_mcucfg_regs, sec_pol_ctl_en13, 0x2634);
716 check_member(mt8186_mcucfg_regs, sec_pol_ctl_en14, 0x2638);
717 check_member(mt8186_mcucfg_regs, sec_pol_ctl_en15, 0x263c);
718 check_member(mt8186_mcucfg_regs, sec_pol_ctl_en16, 0x2640);
719 check_member(mt8186_mcucfg_regs, sec_pol_ctl_en17, 0x2644);
720 check_member(mt8186_mcucfg_regs, sec_pol_ctl_en18, 0x2648);
721 check_member(mt8186_mcucfg_regs, sec_pol_ctl_en19, 0x264c);
722 check_member(mt8186_mcucfg_regs, int_pol_ctl0, 0x2650);
723 check_member(mt8186_mcucfg_regs, int_pol_ctl1, 0x2654);
724 check_member(mt8186_mcucfg_regs, int_pol_ctl2, 0x2658);
725 check_member(mt8186_mcucfg_regs, int_pol_ctl3, 0x265c);
726 check_member(mt8186_mcucfg_regs, int_pol_ctl4, 0x2660);
727 check_member(mt8186_mcucfg_regs, int_pol_ctl5, 0x2664);
728 check_member(mt8186_mcucfg_regs, int_pol_ctl6, 0x2668);
729 check_member(mt8186_mcucfg_regs, int_pol_ctl7, 0x266c);
730 check_member(mt8186_mcucfg_regs, int_pol_ctl8, 0x2670);
731 check_member(mt8186_mcucfg_regs, int_pol_ctl9, 0x2674);
732 check_member(mt8186_mcucfg_regs, int_pol_ctl10, 0x2678);
733 check_member(mt8186_mcucfg_regs, int_pol_ctl11, 0x267c);
734 check_member(mt8186_mcucfg_regs, int_pol_ctl12, 0x2680);
735 check_member(mt8186_mcucfg_regs, int_pol_ctl13, 0x2684);
736 check_member(mt8186_mcucfg_regs, int_pol_ctl14, 0x2688);
737 check_member(mt8186_mcucfg_regs, int_pol_ctl15, 0x268c);
738 check_member(mt8186_mcucfg_regs, int_pol_ctl16, 0x2690);
739 check_member(mt8186_mcucfg_regs, int_pol_ctl17, 0x2694);
740 check_member(mt8186_mcucfg_regs, int_pol_ctl18, 0x2698);
741 check_member(mt8186_mcucfg_regs, int_pol_ctl19, 0x269c);
742 check_member(mt8186_mcucfg_regs, int_msk_ctl0, 0x26a0);
743 check_member(mt8186_mcucfg_regs, int_msk_ctl1, 0x26a4);
744 check_member(mt8186_mcucfg_regs, int_msk_ctl2, 0x26a8);
745 check_member(mt8186_mcucfg_regs, int_msk_ctl3, 0x26ac);
746 check_member(mt8186_mcucfg_regs, int_msk_ctl4, 0x26b0);
747 check_member(mt8186_mcucfg_regs, int_msk_ctl5, 0x26b4);
748 check_member(mt8186_mcucfg_regs, int_msk_ctl6, 0x26b8);
749 check_member(mt8186_mcucfg_regs, int_msk_ctl7, 0x26bc);
750 check_member(mt8186_mcucfg_regs, int_msk_ctl8, 0x26c0);
751 check_member(mt8186_mcucfg_regs, int_msk_ctl9, 0x26c4);
752 check_member(mt8186_mcucfg_regs, int_msk_ctl10, 0x26c8);
753 check_member(mt8186_mcucfg_regs, int_msk_ctl11, 0x26cc);
754 check_member(mt8186_mcucfg_regs, int_msk_ctl12, 0x26d0);
755 check_member(mt8186_mcucfg_regs, int_msk_ctl13, 0x26d4);
756 check_member(mt8186_mcucfg_regs, int_msk_ctl14, 0x26d8);
757 check_member(mt8186_mcucfg_regs, int_msk_ctl15, 0x26dc);
758 check_member(mt8186_mcucfg_regs, int_msk_ctl16, 0x26e0);
759 check_member(mt8186_mcucfg_regs, int_msk_ctl17, 0x26e4);
760 check_member(mt8186_mcucfg_regs, int_msk_ctl18, 0x26e8);
761 check_member(mt8186_mcucfg_regs, int_msk_ctl19, 0x26ec);
762 check_member(mt8186_mcucfg_regs, int_msk_ctl_all, 0x26f4);
763 check_member(mt8186_mcucfg_regs, int_cfg_indirect_access, 0x26f8);
764 check_member(mt8186_mcucfg_regs, int_cfg_direct_access_en, 0x26fc);
765 check_member(mt8186_mcucfg_regs, fcm_spmc_sw_cfg1, 0x2700);
766 check_member(mt8186_mcucfg_regs, fcm_spmc_sw_cfg2, 0x2704);
767 check_member(mt8186_mcucfg_regs, fcm_spmc_wait_cfg, 0x2708);
768 check_member(mt8186_mcucfg_regs, fcm_spmc_sw_pchannel, 0x270c);
769 check_member(mt8186_mcucfg_regs, fcm_spmc_pwr_status, 0x2710);
770 check_member(mt8186_mcucfg_regs, fcm_spmc_off_thres, 0x2714);
771 check_member(mt8186_mcucfg_regs, fcm_spmc_wdt_latch_info, 0x2718);
772 check_member(mt8186_mcucfg_regs, mcusys_spmc_sw_cfg, 0x2740);
773 check_member(mt8186_mcucfg_regs, mcusys_spmc_wait_cfg, 0x2744);
774 check_member(mt8186_mcucfg_regs, mcusys_spmc_pwr_status, 0x2748);
775 check_member(mt8186_mcucfg_regs, cpc_pllbuck_req_ctrl, 0x2800);
776 check_member(mt8186_mcucfg_regs, mcusys_pwr_ctrl, 0x2804);
777 check_member(mt8186_mcucfg_regs, cpusys_pwr_ctrl, 0x2808);
778 check_member(mt8186_mcucfg_regs, sw_gic_wakeup_req, 0x280c);
779 check_member(mt8186_mcucfg_regs, cpc_pllbuck_arb_weight, 0x2810);
780 check_member(mt8186_mcucfg_regs, cpc_flow_ctrl_cfg, 0x2814);
781 check_member(mt8186_mcucfg_regs, cpc_last_core_req, 0x2818);
782 check_member(mt8186_mcucfg_regs, cpc_cpusys_last_core_resp, 0x281c);
783 check_member(mt8186_mcucfg_regs, cpc_mcusys_last_core_resp, 0x2824);
784 check_member(mt8186_mcucfg_regs, cpc_pwr_on_mask, 0x2828);
785 check_member(mt8186_mcucfg_regs, cpc_spmc_pwr_status, 0x2840);
786 check_member(mt8186_mcucfg_regs, cpc_core_cur_fsm, 0x2844);
787 check_member(mt8186_mcucfg_regs, cpc_cpusys_mcusys_cur_fsm, 0x2848);
788 check_member(mt8186_mcucfg_regs, cpc_wakeup_req, 0x284c);
789 check_member(mt8186_mcucfg_regs, cpc_turbo_ctrl, 0x285c);
790 check_member(mt8186_mcucfg_regs, cpc_turbo_gp0_ctrl, 0x2860);
791 check_member(mt8186_mcucfg_regs, cpc_turbo_gp1_ctrl, 0x2864);
792 check_member(mt8186_mcucfg_regs, cpc_turbo_gp2_ctrl, 0x2868);
793 check_member(mt8186_mcucfg_regs, cpc_turbo_pwr_on_mask, 0x286c);
794 check_member(mt8186_mcucfg_regs, cpc_turbo_gp0_req, 0x2870);
795 check_member(mt8186_mcucfg_regs, cpc_turbo_gp1_req, 0x2874);
796 check_member(mt8186_mcucfg_regs, cpc_turbo_gp2_req, 0x2878);
797 check_member(mt8186_mcucfg_regs, cpc_turbo_gp0_resp, 0x2880);
798 check_member(mt8186_mcucfg_regs, cpc_turbo_gp1_resp, 0x2884);
799 check_member(mt8186_mcucfg_regs, cpc_turbo_gp2_resp, 0x2888);
800 check_member(mt8186_mcucfg_regs, cpc_coh_block_thres, 0x288c);
801 check_member(mt8186_mcucfg_regs, cpc_int_status, 0x2890);
802 check_member(mt8186_mcucfg_regs, cpc_int_enable, 0x2894);
803 check_member(mt8186_mcucfg_regs, pllbuck_group_func, 0x2898);
804 check_member(mt8186_mcucfg_regs, cpc_dcm_enable, 0x289c);
805 check_member(mt8186_mcucfg_regs, cpc_pllbuck_state, 0x28a0);
806 check_member(mt8186_mcucfg_regs, cpc_cpu_on_sw_hint, 0x28a4);
807 check_member(mt8186_mcucfg_regs, cpc_cpu_on_sw_hint_set, 0x28a8);
808 check_member(mt8186_mcucfg_regs, cpc_cpu_on_sw_hint_clear, 0x28ac);
809 check_member(mt8186_mcucfg_regs, emi_wfifo, 0x2900);
810 check_member(mt8186_mcucfg_regs, axi1to4_cfg, 0x2904);
811 check_member(mt8186_mcucfg_regs, emi_adb_edge_sel, 0x290c);
812 check_member(mt8186_mcucfg_regs, sclk_cfg_slow_down_ck, 0x2920);
813 check_member(mt8186_mcucfg_regs, mcusys_dbg_mon_sel, 0x2990);
814 check_member(mt8186_mcucfg_regs, mcusys_dbg_mon, 0x2994);
815 check_member(mt8186_mcucfg_regs, gic_acao_ctl0, 0x2a80);
816 check_member(mt8186_mcucfg_regs, gic_acao_ctl1, 0x2a84);
817 check_member(mt8186_mcucfg_regs, gic_acao_ctl2, 0x2a88);
818 check_member(mt8186_mcucfg_regs, spmc_dbg_setting, 0x2b00);
819 check_member(mt8186_mcucfg_regs, kernel_base_l, 0x2b04);
820 check_member(mt8186_mcucfg_regs, kernel_base_h, 0x2b08);
821 check_member(mt8186_mcucfg_regs, systime_base_l, 0x2b0c);
822 check_member(mt8186_mcucfg_regs, systime_base_h, 0x2b10);
823 check_member(mt8186_mcucfg_regs, trace_data_selection, 0x2b14);
824 check_member(mt8186_mcucfg_regs, trace_data_entry0_l, 0x2b20);
825 check_member(mt8186_mcucfg_regs, trace_data_entry0_h, 0x2b24);
826 check_member(mt8186_mcucfg_regs, trace_data_entry1_l, 0x2b28);
827 check_member(mt8186_mcucfg_regs, trace_data_entry1_h, 0x2b2c);
828 check_member(mt8186_mcucfg_regs, trace_data_entry2_l, 0x2b30);
829 check_member(mt8186_mcucfg_regs, trace_data_entry2_h, 0x2b34);
830 check_member(mt8186_mcucfg_regs, trace_data_entry3_l, 0x2b38);
831 check_member(mt8186_mcucfg_regs, trace_data_entry3_h, 0x2b3c);
832 check_member(mt8186_mcucfg_regs, cpu0_on_off_latency, 0x2b40);
833 check_member(mt8186_mcucfg_regs, cpu1_on_off_latency, 0x2b44);
834 check_member(mt8186_mcucfg_regs, cpu2_on_off_latency, 0x2b48);
835 check_member(mt8186_mcucfg_regs, cpu3_on_off_latency, 0x2b4c);
836 check_member(mt8186_mcucfg_regs, cpu4_on_off_latency, 0x2b50);
837 check_member(mt8186_mcucfg_regs, cpu5_on_off_latency, 0x2b54);
838 check_member(mt8186_mcucfg_regs, cpu6_on_off_latency, 0x2b58);
839 check_member(mt8186_mcucfg_regs, cpu7_on_off_latency, 0x2b5c);
840 check_member(mt8186_mcucfg_regs, cluster_off_latency, 0x2b60);
841 check_member(mt8186_mcucfg_regs, cluster_on_latency, 0x2b64);
842 check_member(mt8186_mcucfg_regs, mcusys_on_off_latency, 0x2b68);
843 check_member(mt8186_mcucfg_regs, cluster_off_dormant_counter, 0x2b70);
844 check_member(mt8186_mcucfg_regs, cluster_off_dormant_counter_clear, 0x2b74);
845 check_member(mt8186_mcucfg_regs, cpc_wdt_latch_info1, 0x2b80);
846 check_member(mt8186_mcucfg_regs, cpc_wdt_latch_info2, 0x2b84);
847 check_member(mt8186_mcucfg_regs, cpc_wdt_latch_info3, 0x2b88);
848 check_member(mt8186_mcucfg_regs, cpc_wdt_latch_info4, 0x2b8c);
849 check_member(mt8186_mcucfg_regs, cpc_wdt_latch_info5, 0x2b90);
850 check_member(mt8186_mcucfg_regs, cpc_pmu_ctrl, 0x2b94);
851 check_member(mt8186_mcucfg_regs, cpc_pmu_cnt_clr, 0x2b98);
852 check_member(mt8186_mcucfg_regs, cpc_pmu_cnt0, 0x2b9c);
853 check_member(mt8186_mcucfg_regs, ildo_vproc2_en, 0x2d00);
854 check_member(mt8186_mcucfg_regs, pikachu_event, 0x2e00);
855 check_member(mt8186_mcucfg_regs, pikachu_status, 0x2e04);
856 check_member(mt8186_mcucfg_regs, cpu0_drcc_ao_config, 0x3000);
857 check_member(mt8186_mcucfg_regs, cpu0_resereved_reg, 0x31f8);
858 check_member(mt8186_mcucfg_regs, cpu0_resereved_reg_rd, 0x31fc);
859 check_member(mt8186_mcucfg_regs, cpu1_drcc_ao_config, 0x3200);
860 check_member(mt8186_mcucfg_regs, cpu1_resereved_reg, 0x33f8);
861 check_member(mt8186_mcucfg_regs, cpu1_resereved_reg_rd, 0x33fc);
862 check_member(mt8186_mcucfg_regs, cpu2_drcc_ao_config, 0x3400);
863 check_member(mt8186_mcucfg_regs, cpu2_resereved_reg, 0x35f8);
864 check_member(mt8186_mcucfg_regs, cpu2_resereved_reg_rd, 0x35fc);
865 check_member(mt8186_mcucfg_regs, cpu3_drcc_ao_config, 0x3600);
866 check_member(mt8186_mcucfg_regs, cpu3_resereved_reg, 0x37f8);
867 check_member(mt8186_mcucfg_regs, cpu3_resereved_reg_rd, 0x37fc);
868 check_member(mt8186_mcucfg_regs, cpu4_drcc_ao_config, 0x3800);
869 check_member(mt8186_mcucfg_regs, cpu4_resereved_reg, 0x39f8);
870 check_member(mt8186_mcucfg_regs, cpu4_resereved_reg_rd, 0x39fc);
871 check_member(mt8186_mcucfg_regs, cpu5_drcc_ao_config, 0x3a00);
872 check_member(mt8186_mcucfg_regs, cpu5_resereved_reg, 0x3bf8);
873 check_member(mt8186_mcucfg_regs, cpu5_resereved_reg_rd, 0x3bfc);
874 check_member(mt8186_mcucfg_regs, cpu6_drcc_ao_config, 0x3c00);
875 check_member(mt8186_mcucfg_regs, cpu6_resereved_reg, 0x3df8);
876 check_member(mt8186_mcucfg_regs, cpu6_resereved_reg_rd, 0x3dfc);
877 check_member(mt8186_mcucfg_regs, cpu7_drcc_ao_config, 0x3e00);
878 check_member(mt8186_mcucfg_regs, cpu7_resereved_reg, 0x3ff8);
879 check_member(mt8186_mcucfg_regs, cpu7_resereved_reg_rd, 0x3ffc);
880 check_member(mt8186_mcucfg_regs, mp0_l3_data_ram_delsel, 0x4840);
881 check_member(mt8186_mcucfg_regs, mp0_l3_tag_ram_delsel, 0x4844);
882 check_member(mt8186_mcucfg_regs, mp0_l3_victim_ram_delsel, 0x4848);
883 check_member(mt8186_mcucfg_regs, mp0_l3_scu_sf_ram_delsel, 0x484c);
884 check_member(mt8186_mcucfg_regs, mp0_dcm_cfg0, 0x4880);
885 check_member(mt8186_mcucfg_regs, mp0_dcm_cfg1, 0x4884);
886 check_member(mt8186_mcucfg_regs, mp0_dcm_cfg2, 0x4888);
887 check_member(mt8186_mcucfg_regs, mp0_dcm_cfg3, 0x488c);
888 check_member(mt8186_mcucfg_regs, mp0_dcm_cfg4, 0x4890);
889 check_member(mt8186_mcucfg_regs, mp0_dcm_cfg5, 0x4894);
890 check_member(mt8186_mcucfg_regs, mp0_dcm_cfg6, 0x4898);
891 check_member(mt8186_mcucfg_regs, mp0_dcm_cfg7, 0x489c);
892 check_member(mt8186_mcucfg_regs, mp0_dcm_cfg8, 0x48a0);
893 check_member(mt8186_mcucfg_regs, mp0_l3_cache_parity1, 0x48c0);
894 check_member(mt8186_mcucfg_regs, mp0_l3_cache_parity2, 0x48c4);
895 check_member(mt8186_mcucfg_regs, mp0_l3_cache_parity3, 0x48c8);
896 check_member(mt8186_mcucfg_regs, mp0_cluster_cfg0, 0x48d0);
897 check_member(mt8186_mcucfg_regs, mp0_cluster_cfg4, 0x48e0);
898 check_member(mt8186_mcucfg_regs, mp0_cluster_cfg5, 0x48e4);
899 check_member(mt8186_mcucfg_regs, mp0_cluster_cfg6, 0x48e8);
900 check_member(mt8186_mcucfg_regs, mp0_cluster_cfg7, 0x48ec);
901 check_member(mt8186_mcucfg_regs, mp0_cluster_cfg8, 0x4900);
902 check_member(mt8186_mcucfg_regs, mp0_cluster_cfg9, 0x4904);
903 check_member(mt8186_mcucfg_regs, mp0_cluster_cfg10, 0x4908);
904 check_member(mt8186_mcucfg_regs, mp0_cluster_cfg11, 0x490c);
905 check_member(mt8186_mcucfg_regs, mp0_cluster_cfg12, 0x4910);
906 check_member(mt8186_mcucfg_regs, mp0_cluster_cfg13, 0x4914);
907 check_member(mt8186_mcucfg_regs, mp0_cluster_cfg14, 0x4918);
908 check_member(mt8186_mcucfg_regs, mp0_cluster_cfg15, 0x491c);
909 check_member(mt8186_mcucfg_regs, mp0_cluster_cfg16, 0x4920);
910 check_member(mt8186_mcucfg_regs, mp0_cluster_cfg17, 0x4924);
911 check_member(mt8186_mcucfg_regs, mp0_cluster_cfg18, 0x4928);
912 check_member(mt8186_mcucfg_regs, mp0_cluster_cfg19, 0x492c);
913 check_member(mt8186_mcucfg_regs, mp0_cluster_cfg20, 0x4930);
914 check_member(mt8186_mcucfg_regs, mp0_cluster_cfg21, 0x4934);
915 check_member(mt8186_mcucfg_regs, mp0_cluster_cfg22, 0x4938);
916 check_member(mt8186_mcucfg_regs, mp0_cluster_cfg23, 0x493c);
917 check_member(mt8186_mcucfg_regs, mp0_victim_rd_mask, 0x4944);
918 check_member(mt8186_mcucfg_regs, cpu_type0_spmc0_cfg, 0x4c00);
919 check_member(mt8186_mcucfg_regs, cpu_type0_ram_delsel0_cfg, 0x4c20);
920 check_member(mt8186_mcucfg_regs, cpu_type0_ram_delsel1_cfg, 0x4c24);
921 check_member(mt8186_mcucfg_regs, cpu_type0_ram_delsel2_cfg, 0x4c28);
922 check_member(mt8186_mcucfg_regs, cpu_type1_spmc0_cfg, 0x4d00);
923 check_member(mt8186_mcucfg_regs, cpu_type1_mpmmen, 0x4d10);
924 check_member(mt8186_mcucfg_regs, cpu_type1_ram_delsel0_cfg, 0x4d20);
925 check_member(mt8186_mcucfg_regs, cpu_type1_ram_delsel1_cfg, 0x4d24);
926 check_member(mt8186_mcucfg_regs, cpu_type1_ram_delsel2_cfg, 0x4d28);
927 check_member(mt8186_mcucfg_regs, plldiv_turbo, 0x4e00);
928 check_member(mt8186_mcucfg_regs, plldiv_percore_dfs_1, 0x4e04);
929 check_member(mt8186_mcucfg_regs, plldiv_percore_dfs_2, 0x4e08);
930 check_member(mt8186_mcucfg_regs, plldiv_imax_cg, 0x4e0c);
931 check_member(mt8186_mcucfg_regs, plldiv_imax_int, 0x4e10);
932 check_member(mt8186_mcucfg_regs, plldiv_imax_detector, 0x4e14);
933 check_member(mt8186_mcucfg_regs, plldiv_little_reserved, 0x4e18);
934 check_member(mt8186_mcucfg_regs, plldiv_big_reserved, 0x4e1c);
935 check_member(mt8186_mcucfg_regs, plldiv_bus_reserved, 0x4e20);
936 check_member(mt8186_mcucfg_regs, mcusys_reserved_reg0, 0x7fe0);
937 check_member(mt8186_mcucfg_regs, mcusys_reserved_reg1, 0x7fe4);
938 check_member(mt8186_mcucfg_regs, mcusys_reserved_reg2, 0x7fe8);
939 check_member(mt8186_mcucfg_regs, mcusys_reserved_reg3, 0x7fec);
940 check_member(mt8186_mcucfg_regs, mcusys_reserved_reg0_rd, 0x7ff0);
941 check_member(mt8186_mcucfg_regs, mcusys_reserved_reg1_rd, 0x7ff4);
942 check_member(mt8186_mcucfg_regs, mcusys_reserved_reg2_rd, 0x7ff8);
943 check_member(mt8186_mcucfg_regs, mcusys_reserved_reg3_rd, 0x7ffc);
944 
945 static struct mt8186_mcucfg_regs *const mtk_mcucfg = (void *)MCUCFG_BASE;
946 
947 #endif /* SOC_MEDIATEK_MT8186_MCUCFG_H */
check_member
check_member(mt8173_mcucfg_regs, mcusys_rw_rsvd1, 0x688)
mtk_mcucfg
static struct mt8186_mcucfg_regs *const mtk_mcucfg
Definition: mcucfg.h:945
MCUCFG_BASE
@ MCUCFG_BASE
Definition: addressmap.h:27
u32
uint32_t u32
Definition: stdint.h:51
mt8186_mcucfg_regs
Definition: mcucfg.h:14
mt8186_mcucfg_regs::reserved43
u32 reserved43[1]
Definition: mcucfg.h:227
mt8186_mcucfg_regs::int_pol_ctl4
u32 int_pol_ctl4
Definition: mcucfg.h:264
mt8186_mcucfg_regs::cpc_turbo_gp0_ctrl
u32 cpc_turbo_gp0_ctrl
Definition: mcucfg.h:334
mt8186_mcucfg_regs::l2_parity_clr
u32 l2_parity_clr
Definition: mcucfg.h:36
mt8186_mcucfg_regs::cpc_turbo_gp1_req
u32 cpc_turbo_gp1_req
Definition: mcucfg.h:339
mt8186_mcucfg_regs::reserved86
u32 reserved86[3]
Definition: mcucfg.h:498
mt8186_mcucfg_regs::cci_m0_if
u32 cci_m0_if
Definition: mcucfg.h:84
mt8186_mcucfg_regs::mp_adb_dcm_cfg4
u32 mp_adb_dcm_cfg4
Definition: mcucfg.h:226
mt8186_mcucfg_regs::cpc_turbo_gp2_ctrl
u32 cpc_turbo_gp2_ctrl
Definition: mcucfg.h:336
mt8186_mcucfg_regs::reserved84
u32 reserved84[7]
Definition: mcucfg.h:492
mt8186_mcucfg_regs::mcsi_cfg2
u32 mcsi_cfg2
Definition: mcucfg.h:215
mt8186_mcucfg_regs::cpc_pllbuck_arb_weight
u32 cpc_pllbuck_arb_weight
Definition: mcucfg.h:320
mt8186_mcucfg_regs::adb_bist_cfg1
u32 adb_bist_cfg1
Definition: mcucfg.h:140
mt8186_mcucfg_regs::int_pol_ctl12
u32 int_pol_ctl12
Definition: mcucfg.h:272
mt8186_mcucfg_regs::int_msk_ctl6
u32 int_msk_ctl6
Definition: mcucfg.h:286
mt8186_mcucfg_regs::int_pol_ctl1
u32 int_pol_ctl1
Definition: mcucfg.h:261
mt8186_mcucfg_regs::trace_data_entry1_h
u32 trace_data_entry1_h
Definition: mcucfg.h:379
mt8186_mcucfg_regs::int_pol_ctl14
u32 int_pol_ctl14
Definition: mcucfg.h:274
mt8186_mcucfg_regs::cpc_turbo_gp2_req
u32 cpc_turbo_gp2_req
Definition: mcucfg.h:340
mt8186_mcucfg_regs::reserved54
u32 reserved54[3]
Definition: mcucfg.h:332
mt8186_mcucfg_regs::reserved58
u32 reserved58[4]
Definition: mcucfg.h:359
mt8186_mcucfg_regs::mp0_cluster_cfg10
u32 mp0_cluster_cfg10
Definition: mcucfg.h:474
mt8186_mcucfg_regs::reserved88
u32 reserved88[53]
Definition: mcucfg.h:504
mt8186_mcucfg_regs::int_pol_ctl17
u32 int_pol_ctl17
Definition: mcucfg.h:277
mt8186_mcucfg_regs::dfd_cnt_h
u32 dfd_cnt_h
Definition: mcucfg.h:29
mt8186_mcucfg_regs::etb_cfg0
u32 etb_cfg0
Definition: mcucfg.h:209
mt8186_mcucfg_regs::reserved63
u32 reserved63[1]
Definition: mcucfg.h:395
mt8186_mcucfg_regs::reserved17
u32 reserved17[4]
Definition: mcucfg.h:103
mt8186_mcucfg_regs::cci_m1_if_latch
u32 cci_m1_if_latch
Definition: mcucfg.h:96
mt8186_mcucfg_regs::cpu1_drcc_ao_config
u32 cpu1_drcc_ao_config
Definition: mcucfg.h:417
mt8186_mcucfg_regs::cci_s1_if
u32 cci_s1_if
Definition: mcucfg.h:88
mt8186_mcucfg_regs::cci_m1_if
u32 cci_m1_if
Definition: mcucfg.h:85
mt8186_mcucfg_regs::reserved80
u32 reserved80[3]
Definition: mcucfg.h:466
mt8186_mcucfg_regs::mp0_cpu0_nonwfx_ctrl
u32 mp0_cpu0_nonwfx_ctrl
Definition: mcucfg.h:119
mt8186_mcucfg_regs::mcusys_reserved_reg2
u32 mcusys_reserved_reg2
Definition: mcucfg.h:517
mt8186_mcucfg_regs::mcsi_cfg3
u32 mcsi_cfg3
Definition: mcucfg.h:216
mt8186_mcucfg_regs::cpc_cpusys_mcusys_cur_fsm
u32 cpc_cpusys_mcusys_cur_fsm
Definition: mcucfg.h:330
mt8186_mcucfg_regs::mp_adb_dcm_cfg0
u32 mp_adb_dcm_cfg0
Definition: mcucfg.h:222
mt8186_mcucfg_regs::reserved79
u32 reserved79[1]
Definition: mcucfg.h:464
mt8186_mcucfg_regs::reserved24
u32 reserved24[1667]
Definition: mcucfg.h:145
mt8186_mcucfg_regs::mp0_cluster_cfg19
u32 mp0_cluster_cfg19
Definition: mcucfg.h:483
mt8186_mcucfg_regs::mp0_l3_scu_sf_ram_delsel
u32 mp0_l3_scu_sf_ram_delsel
Definition: mcucfg.h:449
mt8186_mcucfg_regs::reserved18
u32 reserved18[39]
Definition: mcucfg.h:105
mt8186_mcucfg_regs::l2_parity_info1_cpu5
u32 l2_parity_info1_cpu5
Definition: mcucfg.h:47
mt8186_mcucfg_regs::trace_data_entry1_l
u32 trace_data_entry1_l
Definition: mcucfg.h:378
mt8186_mcucfg_regs::l3c_share_cfg1
u32 l3c_share_cfg1
Definition: mcucfg.h:180
mt8186_mcucfg_regs::mp0_l3_cache_parity1
u32 mp0_l3_cache_parity1
Definition: mcucfg.h:461
mt8186_mcucfg_regs::mp0_cpu7_dc_age
u32 mp0_cpu7_dc_age
Definition: mcucfg.h:117
mt8186_mcucfg_regs::cpc_pmu_cnt0
u32 cpc_pmu_cnt0
Definition: mcucfg.h:406
mt8186_mcucfg_regs::mcusys_core_status
u32 mcusys_core_status
Definition: mcucfg.h:186
mt8186_mcucfg_regs::cpc_wakeup_req
u32 cpc_wakeup_req
Definition: mcucfg.h:331
mt8186_mcucfg_regs::apmcu2emi_early_cke_ctl
u32 apmcu2emi_early_cke_ctl
Definition: mcucfg.h:54
mt8186_mcucfg_regs::cci_s4_tra
u32 cci_s4_tra
Definition: mcucfg.h:73
mt8186_mcucfg_regs::mbista_mcsi_sf2_con
u32 mbista_mcsi_sf2_con
Definition: mcucfg.h:18
mt8186_mcucfg_regs::reserved73
u32 reserved73[125]
Definition: mcucfg.h:434
mt8186_mcucfg_regs::cluster_on_latency
u32 cluster_on_latency
Definition: mcucfg.h:393
mt8186_mcucfg_regs::cpc_pmu_ctrl
u32 cpc_pmu_ctrl
Definition: mcucfg.h:404
mt8186_mcucfg_regs::mp0_cluster_cfg20
u32 mp0_cluster_cfg20
Definition: mcucfg.h:484
mt8186_mcucfg_regs::cpc_cpu_on_sw_hint
u32 cpc_cpu_on_sw_hint
Definition: mcucfg.h:351
mt8186_mcucfg_regs::plldiv_percore_dfs_1
u32 plldiv_percore_dfs_1
Definition: mcucfg.h:506
mt8186_mcucfg_regs::cpc_turbo_ctrl
u32 cpc_turbo_ctrl
Definition: mcucfg.h:333
mt8186_mcucfg_regs::reserved27
u32 reserved27[1]
Definition: mcucfg.h:178
mt8186_mcucfg_regs::dfd_v30_base_addr
u32 dfd_v30_base_addr
Definition: mcucfg.h:165
mt8186_mcucfg_regs::int_msk_ctl7
u32 int_msk_ctl7
Definition: mcucfg.h:287
mt8186_mcucfg_regs::mcsi_cfg1
u32 mcsi_cfg1
Definition: mcucfg.h:214
mt8186_mcucfg_regs::l3c_share_status1
u32 l3c_share_status1
Definition: mcucfg.h:107
mt8186_mcucfg_regs::cci_s3_if_latch
u32 cci_s3_if_latch
Definition: mcucfg.h:101
mt8186_mcucfg_regs::mp0_dcm_cfg0
u32 mp0_dcm_cfg0
Definition: mcucfg.h:451
mt8186_mcucfg_regs::mp0_dcm_cfg7
u32 mp0_dcm_cfg7
Definition: mcucfg.h:458
mt8186_mcucfg_regs::reserved19
u32 reserved19[1]
Definition: mcucfg.h:109
mt8186_mcucfg_regs::bus_plldiv_cfg
u32 bus_plldiv_cfg
Definition: mcucfg.h:200
mt8186_mcucfg_regs::plldiv_turbo
u32 plldiv_turbo
Definition: mcucfg.h:505
mt8186_mcucfg_regs::dfd_internal_num_of_test_so_gp
u32 dfd_internal_num_of_test_so_gp
Definition: mcucfg.h:158
mt8186_mcucfg_regs::cpu_type1_ram_delsel2_cfg
u32 cpu_type1_ram_delsel2_cfg
Definition: mcucfg.h:503
mt8186_mcucfg_regs::trace_data_entry0_l
u32 trace_data_entry0_l
Definition: mcucfg.h:376
mt8186_mcucfg_regs::mcusys_reserved_reg1
u32 mcusys_reserved_reg1
Definition: mcucfg.h:516
mt8186_mcucfg_regs::mcusys_reserved_reg0_rd
u32 mcusys_reserved_reg0_rd
Definition: mcucfg.h:519
mt8186_mcucfg_regs::cpu4_resereved_reg_rd
u32 cpu4_resereved_reg_rd
Definition: mcucfg.h:432
mt8186_mcucfg_regs::cpu_type1_spmc0_cfg
u32 cpu_type1_spmc0_cfg
Definition: mcucfg.h:497
mt8186_mcucfg_regs::trace_data_entry2_h
u32 trace_data_entry2_h
Definition: mcucfg.h:381
mt8186_mcucfg_regs::cpc_turbo_pwr_on_mask
u32 cpc_turbo_pwr_on_mask
Definition: mcucfg.h:337
mt8186_mcucfg_regs::dfd_internal_chain_length_3
u32 dfd_internal_chain_length_3
Definition: mcucfg.h:155
mt8186_mcucfg_regs::dfd_v30_ctl
u32 dfd_v30_ctl
Definition: mcucfg.h:164
mt8186_mcucfg_regs::cpu0_resereved_reg_rd
u32 cpu0_resereved_reg_rd
Definition: mcucfg.h:416
mt8186_mcucfg_regs::mp0_cluster_cfg6
u32 mp0_cluster_cfg6
Definition: mcucfg.h:469
mt8186_mcucfg_regs::cpu_plldiv_cfg2
u32 cpu_plldiv_cfg2
Definition: mcucfg.h:198
mt8186_mcucfg_regs::cci_tra_cfg11
u32 cci_tra_cfg11
Definition: mcucfg.h:63
mt8186_mcucfg_regs::mp0_cluster_cfg18
u32 mp0_cluster_cfg18
Definition: mcucfg.h:482
mt8186_mcucfg_regs::reserved14
u32 reserved14[4]
Definition: mcucfg.h:92
mt8186_mcucfg_regs::mp0_cpu4_nonwfx_ctrl
u32 mp0_cpu4_nonwfx_ctrl
Definition: mcucfg.h:127
mt8186_mcucfg_regs::dcc_bus_con0
u32 dcc_bus_con0
Definition: mcucfg.h:236
mt8186_mcucfg_regs::int_pol_ctl13
u32 int_pol_ctl13
Definition: mcucfg.h:273
mt8186_mcucfg_regs::reserved78
u32 reserved78[7]
Definition: mcucfg.h:460
mt8186_mcucfg_regs::cpu_type1_ram_delsel0_cfg
u32 cpu_type1_ram_delsel0_cfg
Definition: mcucfg.h:501
mt8186_mcucfg_regs::mbista_mcsi_sf2_result
u32 mbista_mcsi_sf2_result
Definition: mcucfg.h:19
mt8186_mcucfg_regs::mp_top_dbg_mon_sel
u32 mp_top_dbg_mon_sel
Definition: mcucfg.h:31
mt8186_mcucfg_regs::cci_m0_if_latch
u32 cci_m0_if_latch
Definition: mcucfg.h:95
mt8186_mcucfg_regs::cpc_flow_ctrl_cfg
u32 cpc_flow_ctrl_cfg
Definition: mcucfg.h:321
mt8186_mcucfg_regs::cpusys_pwr_ctrl
u32 cpusys_pwr_ctrl
Definition: mcucfg.h:318
mt8186_mcucfg_regs::mp0_cpu3_dc_age
u32 mp0_cpu3_dc_age
Definition: mcucfg.h:113
mt8186_mcucfg_regs::sec_pol_ctl_en18
u32 sec_pol_ctl_en18
Definition: mcucfg.h:258
mt8186_mcucfg_regs::reserved57
u32 reserved57[1]
Definition: mcucfg.h:357
mt8186_mcucfg_regs::dfd_internal_counter
u32 dfd_internal_counter
Definition: mcucfg.h:147
mt8186_mcucfg_regs::reserved12
u32 reserved12[20]
Definition: mcucfg.h:83
mt8186_mcucfg_regs::ildo_vproc2_en
u32 ildo_vproc2_en
Definition: mcucfg.h:408
mt8186_mcucfg_regs::cpu4_resereved_reg
u32 cpu4_resereved_reg
Definition: mcucfg.h:431
mt8186_mcucfg_regs::int_msk_ctl3
u32 int_msk_ctl3
Definition: mcucfg.h:283
mt8186_mcucfg_regs::dfd_internal_chain_legth_0
u32 dfd_internal_chain_legth_0
Definition: mcucfg.h:149
mt8186_mcucfg_regs::cpc_mcusys_last_core_resp
u32 cpc_mcusys_last_core_resp
Definition: mcucfg.h:325
mt8186_mcucfg_regs::cpc_wdt_latch_info1
u32 cpc_wdt_latch_info1
Definition: mcucfg.h:399
mt8186_mcucfg_regs::reserved34
u32 reserved34[3]
Definition: mcucfg.h:203
mt8186_mcucfg_regs::sec_pol_ctl_en2
u32 sec_pol_ctl_en2
Definition: mcucfg.h:242
mt8186_mcucfg_regs::mp0_cpu2_nonwfx_cnt
u32 mp0_cpu2_nonwfx_cnt
Definition: mcucfg.h:124
mt8186_mcucfg_regs::emi_adb_edge_sel
u32 emi_adb_edge_sel
Definition: mcucfg.h:358
mt8186_mcucfg_regs::reserved41
u32 reserved41[1]
Definition: mcucfg.h:223
mt8186_mcucfg_regs::cluster_off_latency
u32 cluster_off_latency
Definition: mcucfg.h:392
mt8186_mcucfg_regs::mbista_rstb
u32 mbista_rstb
Definition: mcucfg.h:22
mt8186_mcucfg_regs::cci_tra_cfg7
u32 cci_tra_cfg7
Definition: mcucfg.h:59
mt8186_mcucfg_regs::cci_s1_tra_latch
u32 cci_s1_tra_latch
Definition: mcucfg.h:79
mt8186_mcucfg_regs::dfd_internal_shift_clk_ratio
u32 dfd_internal_shift_clk_ratio
Definition: mcucfg.h:150
mt8186_mcucfg_regs::mcsi_ram_delsel0
u32 mcsi_ram_delsel0
Definition: mcucfg.h:204
mt8186_mcucfg_regs::int_cfg_indirect_access
u32 int_cfg_indirect_access
Definition: mcucfg.h:302
mt8186_mcucfg_regs::reserved74
u32 reserved74[125]
Definition: mcucfg.h:438
mt8186_mcucfg_regs::dfd_internal_counter_return
u32 dfd_internal_counter_return
Definition: mcucfg.h:151
mt8186_mcucfg_regs::cci_s2_if_latch
u32 cci_s2_if_latch
Definition: mcucfg.h:100
mt8186_mcucfg_regs::l2_parity_info1_cpu2
u32 l2_parity_info1_cpu2
Definition: mcucfg.h:41
mt8186_mcucfg_regs::reserved72
u32 reserved72[125]
Definition: mcucfg.h:430
mt8186_mcucfg_regs::cpu1_resereved_reg_rd
u32 cpu1_resereved_reg_rd
Definition: mcucfg.h:420
mt8186_mcucfg_regs::mp_misc_dcm_cfg0
u32 mp_misc_dcm_cfg0
Definition: mcucfg.h:228
mt8186_mcucfg_regs::reserved32
u32 reserved32[13]
Definition: mcucfg.h:199
mt8186_mcucfg_regs::trace_data_entry3_l
u32 trace_data_entry3_l
Definition: mcucfg.h:382
mt8186_mcucfg_regs::mcusys_dbg_mon_sel
u32 mcusys_dbg_mon_sel
Definition: mcucfg.h:362
mt8186_mcucfg_regs::dcc_cpu_con2
u32 dcc_cpu_con2
Definition: mcucfg.h:234
mt8186_mcucfg_regs::mbista_etb_con
u32 mbista_etb_con
Definition: mcucfg.h:20
mt8186_mcucfg_regs::cpc_turbo_gp0_req
u32 cpc_turbo_gp0_req
Definition: mcucfg.h:338
mt8186_mcucfg_regs::mcsic_dcm0
u32 mcsic_dcm0
Definition: mcucfg.h:219
mt8186_mcucfg_regs::int_pol_ctl0
u32 int_pol_ctl0
Definition: mcucfg.h:260
mt8186_mcucfg_regs::l2_parity_info1_cpu6
u32 l2_parity_info1_cpu6
Definition: mcucfg.h:49
mt8186_mcucfg_regs::reserved20
u32 reserved20[52]
Definition: mcucfg.h:118
mt8186_mcucfg_regs::reserved4
u32 reserved4[5]
Definition: mcucfg.h:30
mt8186_mcucfg_regs::wfx_ret_met_dbc_sel
u32 wfx_ret_met_dbc_sel
Definition: mcucfg.h:138
mt8186_mcucfg_regs::sec_pol_ctl_en15
u32 sec_pol_ctl_en15
Definition: mcucfg.h:255
mt8186_mcucfg_regs::mcsi_cfg0
u32 mcsi_cfg0
Definition: mcucfg.h:213
mt8186_mcucfg_regs::cpc_cpu_on_sw_hint_set
u32 cpc_cpu_on_sw_hint_set
Definition: mcucfg.h:352
mt8186_mcucfg_regs::reserved55
u32 reserved55[1]
Definition: mcucfg.h:341
mt8186_mcucfg_regs::cci_s4_if_latch
u32 cci_s4_if_latch
Definition: mcucfg.h:102
mt8186_mcucfg_regs::dfd_cnt_l
u32 dfd_cnt_l
Definition: mcucfg.h:28
mt8186_mcucfg_regs::reserved8
u32 reserved8[51]
Definition: mcucfg.h:65
mt8186_mcucfg_regs::udi_cfg1
u32 udi_cfg1
Definition: mcucfg.h:184
mt8186_mcucfg_regs::cpc_int_status
u32 cpc_int_status
Definition: mcucfg.h:346
mt8186_mcucfg_regs::dfd_test_si_1
u32 dfd_test_si_1
Definition: mcucfg.h:169
mt8186_mcucfg_regs::reserved75
u32 reserved75[125]
Definition: mcucfg.h:442
mt8186_mcucfg_regs::sec_pol_ctl_en8
u32 sec_pol_ctl_en8
Definition: mcucfg.h:248
mt8186_mcucfg_regs::reserved42
u32 reserved42[1]
Definition: mcucfg.h:225
mt8186_mcucfg_regs::sec_pol_ctl_en11
u32 sec_pol_ctl_en11
Definition: mcucfg.h:251
mt8186_mcucfg_regs::sec_pol_ctl_en17
u32 sec_pol_ctl_en17
Definition: mcucfg.h:257
mt8186_mcucfg_regs::dfd_power_ctl
u32 dfd_power_ctl
Definition: mcucfg.h:166
mt8186_mcucfg_regs::reserved22
u32 reserved22[3]
Definition: mcucfg.h:137
mt8186_mcucfg_regs::l2_parity_info2_cpu0
u32 l2_parity_info2_cpu0
Definition: mcucfg.h:38
mt8186_mcucfg_regs::mp0_cluster_cfg9
u32 mp0_cluster_cfg9
Definition: mcucfg.h:473
mt8186_mcucfg_regs::l2_parity_info1_cpu7
u32 l2_parity_info1_cpu7
Definition: mcucfg.h:51
mt8186_mcucfg_regs::kernel_base_l
u32 kernel_base_l
Definition: mcucfg.h:370
mt8186_mcucfg_regs::cpc_wdt_latch_info2
u32 cpc_wdt_latch_info2
Definition: mcucfg.h:400
mt8186_mcucfg_regs::cci_s4_if
u32 cci_s4_if
Definition: mcucfg.h:91
mt8186_mcucfg_regs::reserved26
u32 reserved26[64]
Definition: mcucfg.h:174
mt8186_mcucfg_regs::int_pol_ctl11
u32 int_pol_ctl11
Definition: mcucfg.h:271
mt8186_mcucfg_regs::gic_acao_ctl0
u32 gic_acao_ctl0
Definition: mcucfg.h:365
mt8186_mcucfg_regs::plldiv_big_reserved
u32 plldiv_big_reserved
Definition: mcucfg.h:512
mt8186_mcucfg_regs::cpu3_resereved_reg_rd
u32 cpu3_resereved_reg_rd
Definition: mcucfg.h:428
mt8186_mcucfg_regs::mp0_victim_rd_mask
u32 mp0_victim_rd_mask
Definition: mcucfg.h:489
mt8186_mcucfg_regs::etb_ram_delsel0
u32 etb_ram_delsel0
Definition: mcucfg.h:207
mt8186_mcucfg_regs::mp0_dcm_cfg5
u32 mp0_dcm_cfg5
Definition: mcucfg.h:456
mt8186_mcucfg_regs::cpu2_resereved_reg
u32 cpu2_resereved_reg
Definition: mcucfg.h:423
mt8186_mcucfg_regs::cci_periph_base
u32 cci_periph_base
Definition: mcucfg.h:191
mt8186_mcucfg_regs::cci_s1_tra
u32 cci_s1_tra
Definition: mcucfg.h:70
mt8186_mcucfg_regs::mp0_cpu1_nonwfx_ctrl
u32 mp0_cpu1_nonwfx_ctrl
Definition: mcucfg.h:121
mt8186_mcucfg_regs::reserved6
u32 reserved6[10]
Definition: mcucfg.h:53
mt8186_mcucfg_regs::l2_parity_info1_cpu4
u32 l2_parity_info1_cpu4
Definition: mcucfg.h:45
mt8186_mcucfg_regs::fcm_spmc_sw_pchannel
u32 fcm_spmc_sw_pchannel
Definition: mcucfg.h:307
mt8186_mcucfg_regs::mcusys_dcm_cfg0
u32 mcusys_dcm_cfg0
Definition: mcucfg.h:238
mt8186_mcucfg_regs::reserved53
u32 reserved53[5]
Definition: mcucfg.h:327
mt8186_mcucfg_regs::int_msk_ctl14
u32 int_msk_ctl14
Definition: mcucfg.h:294
mt8186_mcucfg_regs::mp0_l3_tag_ram_delsel
u32 mp0_l3_tag_ram_delsel
Definition: mcucfg.h:447
mt8186_mcucfg_regs::reserved67
u32 reserved67[126]
Definition: mcucfg.h:412
mt8186_mcucfg_regs::mcusys_spmc_wait_cfg
u32 mcusys_spmc_wait_cfg
Definition: mcucfg.h:313
mt8186_mcucfg_regs::fcm_spmc_sw_cfg2
u32 fcm_spmc_sw_cfg2
Definition: mcucfg.h:305
mt8186_mcucfg_regs::dfd_sram_base
u32 dfd_sram_base
Definition: mcucfg.h:193
mt8186_mcucfg_regs::dfd_internal_test_so_1
u32 dfd_internal_test_so_1
Definition: mcucfg.h:157
mt8186_mcucfg_regs::int_msk_ctl17
u32 int_msk_ctl17
Definition: mcucfg.h:297
mt8186_mcucfg_regs::mcusys_pinmux
u32 mcusys_pinmux
Definition: mcucfg.h:177
mt8186_mcucfg_regs::cluster_off_dormant_counter
u32 cluster_off_dormant_counter
Definition: mcucfg.h:396
mt8186_mcucfg_regs::int_msk_ctl16
u32 int_msk_ctl16
Definition: mcucfg.h:296
mt8186_mcucfg_regs::cpu1_on_off_latency
u32 cpu1_on_off_latency
Definition: mcucfg.h:385
mt8186_mcucfg_regs::reserved37
u32 reserved37[31]
Definition: mcucfg.h:210
mt8186_mcucfg_regs::cpu_type0_spmc0_cfg
u32 cpu_type0_spmc0_cfg
Definition: mcucfg.h:491
mt8186_mcucfg_regs::cpu_plldiv_cfg1
u32 cpu_plldiv_cfg1
Definition: mcucfg.h:197
mt8186_mcucfg_regs::dfd_internal_mask_out
u32 dfd_internal_mask_out
Definition: mcucfg.h:160
mt8186_mcucfg_regs::dfd_hw_trigger_mask
u32 dfd_hw_trigger_mask
Definition: mcucfg.h:173
mt8186_mcucfg_regs::cpu7_resereved_reg_rd
u32 cpu7_resereved_reg_rd
Definition: mcucfg.h:444
mt8186_mcucfg_regs::reserved45
u32 reserved45[15]
Definition: mcucfg.h:231
mt8186_mcucfg_regs::mp0_cluster_cfg17
u32 mp0_cluster_cfg17
Definition: mcucfg.h:481
mt8186_mcucfg_regs::reserved2
u32 reserved2[2]
Definition: mcucfg.h:24
mt8186_mcucfg_regs::reserved62
u32 reserved62[2]
Definition: mcucfg.h:375
mt8186_mcucfg_regs::mp0_cluster_cfg8
u32 mp0_cluster_cfg8
Definition: mcucfg.h:472
mt8186_mcucfg_regs::reserved60
u32 reserved60[58]
Definition: mcucfg.h:364
mt8186_mcucfg_regs::reserved39
u32 reserved39[7]
Definition: mcucfg.h:218
mt8186_mcucfg_regs::mcusys_reserved_reg1_rd
u32 mcusys_reserved_reg1_rd
Definition: mcucfg.h:520
mt8186_mcucfg_regs::cpu6_on_off_latency
u32 cpu6_on_off_latency
Definition: mcucfg.h:390
mt8186_mcucfg_regs::mp0_cluster_cfg0
u32 mp0_cluster_cfg0
Definition: mcucfg.h:465
mt8186_mcucfg_regs::mcusys_spmc_pwr_status
u32 mcusys_spmc_pwr_status
Definition: mcucfg.h:314
mt8186_mcucfg_regs::kernel_base_h
u32 kernel_base_h
Definition: mcucfg.h:371
mt8186_mcucfg_regs::mp0_cpu7_nonwfx_cnt
u32 mp0_cpu7_nonwfx_cnt
Definition: mcucfg.h:134
mt8186_mcucfg_regs::int_msk_ctl11
u32 int_msk_ctl11
Definition: mcucfg.h:291
mt8186_mcucfg_regs::fcm_spmc_sw_cfg1
u32 fcm_spmc_sw_cfg1
Definition: mcucfg.h:304
mt8186_mcucfg_regs::dfd_internal_ctl
u32 dfd_internal_ctl
Definition: mcucfg.h:146
mt8186_mcucfg_regs::reserved51
u32 reserved51[45]
Definition: mcucfg.h:315
mt8186_mcucfg_regs::reserved50
u32 reserved50[9]
Definition: mcucfg.h:311
mt8186_mcucfg_regs::l3c_share_status2
u32 l3c_share_status2
Definition: mcucfg.h:108
mt8186_mcucfg_regs::reserved64
u32 reserved64[2]
Definition: mcucfg.h:398
mt8186_mcucfg_regs::reserved87
u32 reserved87[3]
Definition: mcucfg.h:500
mt8186_mcucfg_regs::dcc_cpu_con1
u32 dcc_cpu_con1
Definition: mcucfg.h:233
mt8186_mcucfg_regs::dfd_internal_chain_length_2
u32 dfd_internal_chain_length_2
Definition: mcucfg.h:154
mt8186_mcucfg_regs::dfd_status_clean
u32 dfd_status_clean
Definition: mcucfg.h:170
mt8186_mcucfg_regs::adb_bist_cfg3_go
u32 adb_bist_cfg3_go
Definition: mcucfg.h:142
mt8186_mcucfg_regs::dfd_internal_chain_length_1
u32 dfd_internal_chain_length_1
Definition: mcucfg.h:153
mt8186_mcucfg_regs::plldiv_imax_cg
u32 plldiv_imax_cg
Definition: mcucfg.h:508
mt8186_mcucfg_regs::int_pol_ctl7
u32 int_pol_ctl7
Definition: mcucfg.h:267
mt8186_mcucfg_regs::cpu6_resereved_reg_rd
u32 cpu6_resereved_reg_rd
Definition: mcucfg.h:440
mt8186_mcucfg_regs::mp0_cpu1_nonwfx_cnt
u32 mp0_cpu1_nonwfx_cnt
Definition: mcucfg.h:122
mt8186_mcucfg_regs::l3c_share_status0
u32 l3c_share_status0
Definition: mcucfg.h:106
mt8186_mcucfg_regs::trace_data_selection
u32 trace_data_selection
Definition: mcucfg.h:374
mt8186_mcucfg_regs::cpu2_resereved_reg_rd
u32 cpu2_resereved_reg_rd
Definition: mcucfg.h:424
mt8186_mcucfg_regs::cpu7_resereved_reg
u32 cpu7_resereved_reg
Definition: mcucfg.h:443
mt8186_mcucfg_regs::cci_s1_if_latch
u32 cci_s1_if_latch
Definition: mcucfg.h:99
mt8186_mcucfg_regs::cpc_turbo_gp0_resp
u32 cpc_turbo_gp0_resp
Definition: mcucfg.h:342
mt8186_mcucfg_regs::reserved25
u32 reserved25[21]
Definition: mcucfg.h:172
mt8186_mcucfg_regs::cpu5_on_off_latency
u32 cpu5_on_off_latency
Definition: mcucfg.h:389
mt8186_mcucfg_regs::spmc_dbg_setting
u32 spmc_dbg_setting
Definition: mcucfg.h:369
mt8186_mcucfg_regs::cpu0_resereved_reg
u32 cpu0_resereved_reg
Definition: mcucfg.h:415
mt8186_mcucfg_regs::reserved13
u32 reserved13[5]
Definition: mcucfg.h:87
mt8186_mcucfg_regs::cci_m0_tra
u32 cci_m0_tra
Definition: mcucfg.h:66
mt8186_mcucfg_regs::dfd_internal_mcsi_sel_status
u32 dfd_internal_mcsi_sel_status
Definition: mcucfg.h:163
mt8186_mcucfg_regs::int_msk_ctl10
u32 int_msk_ctl10
Definition: mcucfg.h:290
mt8186_mcucfg_regs::int_pol_ctl15
u32 int_pol_ctl15
Definition: mcucfg.h:275
mt8186_mcucfg_regs::sec_pol_ctl_en14
u32 sec_pol_ctl_en14
Definition: mcucfg.h:254
mt8186_mcucfg_regs::mp0_dcm_cfg6
u32 mp0_dcm_cfg6
Definition: mcucfg.h:457
mt8186_mcucfg_regs::reserved3
u32 reserved3[3]
Definition: mcucfg.h:26
mt8186_mcucfg_regs::cci_periph_infra_base
u32 cci_periph_infra_base
Definition: mcucfg.h:192
mt8186_mcucfg_regs::mp0_l3_cache_parity2
u32 mp0_l3_cache_parity2
Definition: mcucfg.h:462
mt8186_mcucfg_regs::mcusys_base
u32 mcusys_base
Definition: mcucfg.h:188
mt8186_mcucfg_regs::mp0_dcm_cfg4
u32 mp0_dcm_cfg4
Definition: mcucfg.h:455
mt8186_mcucfg_regs::int_msk_ctl2
u32 int_msk_ctl2
Definition: mcucfg.h:282
mt8186_mcucfg_regs::reserved66
u32 reserved66[63]
Definition: mcucfg.h:409
mt8186_mcucfg_regs::mp0_l3_cache_parity3
u32 mp0_l3_cache_parity3
Definition: mcucfg.h:463
mt8186_mcucfg_regs::sec_pol_ctl_en1
u32 sec_pol_ctl_en1
Definition: mcucfg.h:241
mt8186_mcucfg_regs::mp0_cpu0_dc_age
u32 mp0_cpu0_dc_age
Definition: mcucfg.h:110
mt8186_mcucfg_regs::cci_m1_tra
u32 cci_m1_tra
Definition: mcucfg.h:67
mt8186_mcucfg_regs::mbista_all_result
u32 mbista_all_result
Definition: mcucfg.h:23
mt8186_mcucfg_regs::plldiv_bus_reserved
u32 plldiv_bus_reserved
Definition: mcucfg.h:513
mt8186_mcucfg_regs::cpc_int_enable
u32 cpc_int_enable
Definition: mcucfg.h:347
mt8186_mcucfg_regs::cpc_pwr_on_mask
u32 cpc_pwr_on_mask
Definition: mcucfg.h:326
mt8186_mcucfg_regs::mbist_trigger_mux_ctl
u32 mbist_trigger_mux_ctl
Definition: mcucfg.h:25
mt8186_mcucfg_regs::cci_tra_cfg12
u32 cci_tra_cfg12
Definition: mcucfg.h:64
mt8186_mcucfg_regs::cpc_cpusys_last_core_resp
u32 cpc_cpusys_last_core_resp
Definition: mcucfg.h:323
mt8186_mcucfg_regs::cpu0_on_off_latency
u32 cpu0_on_off_latency
Definition: mcucfg.h:384
mt8186_mcucfg_regs::mp0_l3_victim_ram_delsel
u32 mp0_l3_victim_ram_delsel
Definition: mcucfg.h:448
mt8186_mcucfg_regs::int_msk_ctl1
u32 int_msk_ctl1
Definition: mcucfg.h:281
mt8186_mcucfg_regs::int_pol_ctl5
u32 int_pol_ctl5
Definition: mcucfg.h:265
mt8186_mcucfg_regs::cpc_pmu_cnt_clr
u32 cpc_pmu_cnt_clr
Definition: mcucfg.h:405
mt8186_mcucfg_regs::pllbuck_group_func
u32 pllbuck_group_func
Definition: mcucfg.h:348
mt8186_mcucfg_regs::cpu_type0_ram_delsel1_cfg
u32 cpu_type0_ram_delsel1_cfg
Definition: mcucfg.h:494
mt8186_mcucfg_regs::sec_pol_ctl_en12
u32 sec_pol_ctl_en12
Definition: mcucfg.h:252
mt8186_mcucfg_regs::cpc_coh_block_thres
u32 cpc_coh_block_thres
Definition: mcucfg.h:345
mt8186_mcucfg_regs::cci_s4_tra_latch
u32 cci_s4_tra_latch
Definition: mcucfg.h:82
mt8186_mcucfg_regs::cpu_type0_ram_delsel2_cfg
u32 cpu_type0_ram_delsel2_cfg
Definition: mcucfg.h:495
mt8186_mcucfg_regs::cpc_core_cur_fsm
u32 cpc_core_cur_fsm
Definition: mcucfg.h:329
mt8186_mcucfg_regs::reserved59
u32 reserved59[27]
Definition: mcucfg.h:361
mt8186_mcucfg_regs::cpu3_on_off_latency
u32 cpu3_on_off_latency
Definition: mcucfg.h:387
mt8186_mcucfg_regs::plldiv_imax_int
u32 plldiv_imax_int
Definition: mcucfg.h:509
mt8186_mcucfg_regs::int_cfg_direct_access_en
u32 int_cfg_direct_access_en
Definition: mcucfg.h:303
mt8186_mcucfg_regs::mcusys_dbg_mon
u32 mcusys_dbg_mon
Definition: mcucfg.h:363
mt8186_mcucfg_regs::int_msk_ctl5
u32 int_msk_ctl5
Definition: mcucfg.h:285
mt8186_mcucfg_regs::reserved77
u32 reserved77[12]
Definition: mcucfg.h:450
mt8186_mcucfg_regs::cci_tra_cfg8
u32 cci_tra_cfg8
Definition: mcucfg.h:60
mt8186_mcucfg_regs::reserved38
u32 reserved38[3]
Definition: mcucfg.h:212
mt8186_mcucfg_regs::cci_tra_cfg0
u32 cci_tra_cfg0
Definition: mcucfg.h:55
mt8186_mcucfg_regs::l3c_share_cfg2
u32 l3c_share_cfg2
Definition: mcucfg.h:181
mt8186_mcucfg_regs::l2_parity_info1_cpu3
u32 l2_parity_info1_cpu3
Definition: mcucfg.h:43
mt8186_mcucfg_regs::cci_s2_tra_latch
u32 cci_s2_tra_latch
Definition: mcucfg.h:80
mt8186_mcucfg_regs::reserved7
u32 reserved7[4]
Definition: mcucfg.h:56
mt8186_mcucfg_regs::dfd_test_si_0
u32 dfd_test_si_0
Definition: mcucfg.h:168
mt8186_mcucfg_regs::reserved10
u32 reserved10[4]
Definition: mcucfg.h:74
mt8186_mcucfg_regs::mp0_cluster_cfg12
u32 mp0_cluster_cfg12
Definition: mcucfg.h:476
mt8186_mcucfg_regs::axi1to4_cfg
u32 axi1to4_cfg
Definition: mcucfg.h:356
mt8186_mcucfg_regs::reserved15
u32 reserved15[7]
Definition: mcucfg.h:94
mt8186_mcucfg_regs::dfd_status_return
u32 dfd_status_return
Definition: mcucfg.h:171
mt8186_mcucfg_regs::reserved30
u32 reserved30[11]
Definition: mcucfg.h:187
mt8186_mcucfg_regs::mp0_cluster_cfg23
u32 mp0_cluster_cfg23
Definition: mcucfg.h:487
mt8186_mcucfg_regs::cpu4_on_off_latency
u32 cpu4_on_off_latency
Definition: mcucfg.h:388
mt8186_mcucfg_regs::reserved49
u32 reserved49[1]
Definition: mcucfg.h:300
mt8186_mcucfg_regs::fcm_spmc_off_thres
u32 fcm_spmc_off_thres
Definition: mcucfg.h:309
mt8186_mcucfg_regs::int_msk_ctl19
u32 int_msk_ctl19
Definition: mcucfg.h:299
mt8186_mcucfg_regs::l2_parity_info2_cpu2
u32 l2_parity_info2_cpu2
Definition: mcucfg.h:42
mt8186_mcucfg_regs::sec_pol_ctl_en6
u32 sec_pol_ctl_en6
Definition: mcucfg.h:246
mt8186_mcucfg_regs::sw_gic_wakeup_req
u32 sw_gic_wakeup_req
Definition: mcucfg.h:319
mt8186_mcucfg_regs::cpu5_resereved_reg_rd
u32 cpu5_resereved_reg_rd
Definition: mcucfg.h:436
mt8186_mcucfg_regs::mp0_cluster_cfg7
u32 mp0_cluster_cfg7
Definition: mcucfg.h:470
mt8186_mcucfg_regs::cpc_turbo_gp1_ctrl
u32 cpc_turbo_gp1_ctrl
Definition: mcucfg.h:335
mt8186_mcucfg_regs::reserved5
u32 reserved5[8]
Definition: mcucfg.h:35
mt8186_mcucfg_regs::systime_base_l
u32 systime_base_l
Definition: mcucfg.h:372
mt8186_mcucfg_regs::dfd_reset_on
u32 dfd_reset_on
Definition: mcucfg.h:167
mt8186_mcucfg_regs::cci_tra_cfg10
u32 cci_tra_cfg10
Definition: mcucfg.h:62
mt8186_mcucfg_regs::mcusys_reserved_reg3
u32 mcusys_reserved_reg3
Definition: mcucfg.h:518
mt8186_mcucfg_regs::int_msk_ctl8
u32 int_msk_ctl8
Definition: mcucfg.h:288
mt8186_mcucfg_regs::reserved28
u32 reserved28[1]
Definition: mcucfg.h:182
mt8186_mcucfg_regs::sec_pol_ctl_en0
u32 sec_pol_ctl_en0
Definition: mcucfg.h:240
mt8186_mcucfg_regs::gic_acao_ctl2
u32 gic_acao_ctl2
Definition: mcucfg.h:367
mt8186_mcucfg_regs::reserved31
u32 reserved31[9]
Definition: mcucfg.h:195
mt8186_mcucfg_regs::cpc_pllbuck_req_ctrl
u32 cpc_pllbuck_req_ctrl
Definition: mcucfg.h:316
mt8186_mcucfg_regs::adb_bist_pass
u32 adb_bist_pass
Definition: mcucfg.h:144
mt8186_mcucfg_regs::adb_bist_done
u32 adb_bist_done
Definition: mcucfg.h:143
mt8186_mcucfg_regs::cpu0_drcc_ao_config
u32 cpu0_drcc_ao_config
Definition: mcucfg.h:413
mt8186_mcucfg_regs::mp0_dcm_cfg2
u32 mp0_dcm_cfg2
Definition: mcucfg.h:453
mt8186_mcucfg_regs::systime_base_h
u32 systime_base_h
Definition: mcucfg.h:373
mt8186_mcucfg_regs::sec_pol_ctl_en7
u32 sec_pol_ctl_en7
Definition: mcucfg.h:247
mt8186_mcucfg_regs::sclk_cfg_slow_down_ck
u32 sclk_cfg_slow_down_ck
Definition: mcucfg.h:360
mt8186_mcucfg_regs::reserved71
u32 reserved71[125]
Definition: mcucfg.h:426
mt8186_mcucfg_regs::dfd_internal_mcsi
u32 dfd_internal_mcsi
Definition: mcucfg.h:162
mt8186_mcucfg_regs::int_pol_ctl6
u32 int_pol_ctl6
Definition: mcucfg.h:266
mt8186_mcucfg_regs::mp0_cpu2_dc_age
u32 mp0_cpu2_dc_age
Definition: mcucfg.h:112
mt8186_mcucfg_regs::cpc_cpu_on_sw_hint_clear
u32 cpc_cpu_on_sw_hint_clear
Definition: mcucfg.h:353
mt8186_mcucfg_regs::int_msk_ctl15
u32 int_msk_ctl15
Definition: mcucfg.h:295
mt8186_mcucfg_regs::sec_pol_ctl_en9
u32 sec_pol_ctl_en9
Definition: mcucfg.h:249
mt8186_mcucfg_regs::mp0_ses_apb_trig
u32 mp0_ses_apb_trig
Definition: mcucfg.h:136
mt8186_mcucfg_regs::mp0_cpu6_dc_age
u32 mp0_cpu6_dc_age
Definition: mcucfg.h:116
mt8186_mcucfg_regs::cpu2_on_off_latency
u32 cpu2_on_off_latency
Definition: mcucfg.h:386
mt8186_mcucfg_regs::mp0_dcm_cfg1
u32 mp0_dcm_cfg1
Definition: mcucfg.h:452
mt8186_mcucfg_regs::sec_pol_ctl_en4
u32 sec_pol_ctl_en4
Definition: mcucfg.h:244
mt8186_mcucfg_regs::sec_pol_ctl_en5
u32 sec_pol_ctl_en5
Definition: mcucfg.h:245
mt8186_mcucfg_regs::cci_s3_tra
u32 cci_s3_tra
Definition: mcucfg.h:72
mt8186_mcucfg_regs::int_pol_ctl18
u32 int_pol_ctl18
Definition: mcucfg.h:278
mt8186_mcucfg_regs::mp_adb_dcm_cfg2
u32 mp_adb_dcm_cfg2
Definition: mcucfg.h:224
mt8186_mcucfg_regs::cpc_wdt_latch_info4
u32 cpc_wdt_latch_info4
Definition: mcucfg.h:402
mt8186_mcucfg_regs::l2_parity_info1_cpu0
u32 l2_parity_info1_cpu0
Definition: mcucfg.h:37
mt8186_mcucfg_regs::mp0_cluster_cfg14
u32 mp0_cluster_cfg14
Definition: mcucfg.h:478
mt8186_mcucfg_regs::cpc_dcm_enable
u32 cpc_dcm_enable
Definition: mcucfg.h:349
mt8186_mcucfg_regs::reserved23
u32 reserved23[3]
Definition: mcucfg.h:139
mt8186_mcucfg_regs::dfd_internal_sw_ns_trigger
u32 dfd_internal_sw_ns_trigger
Definition: mcucfg.h:161
mt8186_mcucfg_regs::cci_m2_if_latch
u32 cci_m2_if_latch
Definition: mcucfg.h:97
mt8186_mcucfg_regs::fcm_spmc_pwr_status
u32 fcm_spmc_pwr_status
Definition: mcucfg.h:308
mt8186_mcucfg_regs::trace_data_entry3_h
u32 trace_data_entry3_h
Definition: mcucfg.h:383
mt8186_mcucfg_regs::mcusys_reserved_reg0
u32 mcusys_reserved_reg0
Definition: mcucfg.h:515
mt8186_mcucfg_regs::reserved9
u32 reserved9[5]
Definition: mcucfg.h:69
mt8186_mcucfg_regs::cluster_off_dormant_counter_clear
u32 cluster_off_dormant_counter_clear
Definition: mcucfg.h:397
mt8186_mcucfg_regs::dcc_cpu_con0
u32 dcc_cpu_con0
Definition: mcucfg.h:232
mt8186_mcucfg_regs::plldiv_percore_dfs_2
u32 plldiv_percore_dfs_2
Definition: mcucfg.h:507
mt8186_mcucfg_regs::int_msk_ctl0
u32 int_msk_ctl0
Definition: mcucfg.h:280
mt8186_mcucfg_regs::sec_pol_ctl_en16
u32 sec_pol_ctl_en16
Definition: mcucfg.h:256
mt8186_mcucfg_regs::cpu_type0_ram_delsel0_cfg
u32 cpu_type0_ram_delsel0_cfg
Definition: mcucfg.h:493
mt8186_mcucfg_regs::cpc_pllbuck_state
u32 cpc_pllbuck_state
Definition: mcucfg.h:350
mt8186_mcucfg_regs::cpc_wdt_latch_info3
u32 cpc_wdt_latch_info3
Definition: mcucfg.h:401
mt8186_mcucfg_regs::mp0_cpu6_nonwfx_cnt
u32 mp0_cpu6_nonwfx_cnt
Definition: mcucfg.h:132
mt8186_mcucfg_regs::plldiv_imax_detector
u32 plldiv_imax_detector
Definition: mcucfg.h:510
mt8186_mcucfg_regs::adb_bist_cfg2_md
u32 adb_bist_cfg2_md
Definition: mcucfg.h:141
mt8186_mcucfg_regs::int_pol_ctl3
u32 int_pol_ctl3
Definition: mcucfg.h:263
mt8186_mcucfg_regs::mp0_cpu0_nonwfx_cnt
u32 mp0_cpu0_nonwfx_cnt
Definition: mcucfg.h:120
mt8186_mcucfg_regs::mp0_cluster_cfg22
u32 mp0_cluster_cfg22
Definition: mcucfg.h:486
mt8186_mcucfg_regs::reserved52
u32 reserved52[1]
Definition: mcucfg.h:324
mt8186_mcucfg_regs::l3c_mm_sram_base
u32 l3c_mm_sram_base
Definition: mcucfg.h:194
mt8186_mcucfg_regs::gic_acao_ctl1
u32 gic_acao_ctl1
Definition: mcucfg.h:366
mt8186_mcucfg_regs::sec_pol_ctl_en10
u32 sec_pol_ctl_en10
Definition: mcucfg.h:250
mt8186_mcucfg_regs::mbista_mcsi_sf1_result
u32 mbista_mcsi_sf1_result
Definition: mcucfg.h:17
mt8186_mcucfg_regs::etb_ck_ctl
u32 etb_ck_ctl
Definition: mcucfg.h:230
mt8186_mcucfg_regs::reserved85
u32 reserved85[53]
Definition: mcucfg.h:496
mt8186_mcucfg_regs::int_msk_ctl12
u32 int_msk_ctl12
Definition: mcucfg.h:292
mt8186_mcucfg_regs::mp0_cpu7_nonwfx_ctrl
u32 mp0_cpu7_nonwfx_ctrl
Definition: mcucfg.h:133
mt8186_mcucfg_regs::udi_cfg0
u32 udi_cfg0
Definition: mcucfg.h:183
mt8186_mcucfg_regs::reserved16
u32 reserved16[5]
Definition: mcucfg.h:98
mt8186_mcucfg_regs::cpu6_drcc_ao_config
u32 cpu6_drcc_ao_config
Definition: mcucfg.h:437
mt8186_mcucfg_regs::mp0_cluster_cfg11
u32 mp0_cluster_cfg11
Definition: mcucfg.h:475
mt8186_mcucfg_regs::mbista_mcsi_sf1_con
u32 mbista_mcsi_sf1_con
Definition: mcucfg.h:16
mt8186_mcucfg_regs::reserved40
u32 reserved40[46]
Definition: mcucfg.h:221
mt8186_mcucfg_regs::cpc_wdt_latch_info5
u32 cpc_wdt_latch_info5
Definition: mcucfg.h:403
mt8186_mcucfg_regs::mp0_cpu5_nonwfx_ctrl
u32 mp0_cpu5_nonwfx_ctrl
Definition: mcucfg.h:129
mt8186_mcucfg_regs::mp0_cluster_cfg16
u32 mp0_cluster_cfg16
Definition: mcucfg.h:480
mt8186_mcucfg_regs::cci_s3_tra_latch
u32 cci_s3_tra_latch
Definition: mcucfg.h:81
mt8186_mcucfg_regs::reserved68
u32 reserved68[125]
Definition: mcucfg.h:414
mt8186_mcucfg_regs::reserved44
u32 reserved44[9]
Definition: mcucfg.h:229
mt8186_mcucfg_regs::reserved11
u32 reserved11[5]
Definition: mcucfg.h:78
mt8186_mcucfg_regs::l2_parity_info1_cpu1
u32 l2_parity_info1_cpu1
Definition: mcucfg.h:39
mt8186_mcucfg_regs::reserved70
u32 reserved70[125]
Definition: mcucfg.h:422
mt8186_mcucfg_regs::reserved65
u32 reserved65[88]
Definition: mcucfg.h:407
mt8186_mcucfg_regs::cci_s2_tra
u32 cci_s2_tra
Definition: mcucfg.h:71
mt8186_mcucfg_regs::cpu_type1_mpmmen
u32 cpu_type1_mpmmen
Definition: mcucfg.h:499
mt8186_mcucfg_regs::l2_parity_info2_cpu7
u32 l2_parity_info2_cpu7
Definition: mcucfg.h:52
mt8186_mcucfg_regs::trace_data_entry2_l
u32 trace_data_entry2_l
Definition: mcucfg.h:380
mt8186_mcucfg_regs::mcusys_pwr_ctrl
u32 mcusys_pwr_ctrl
Definition: mcucfg.h:317
mt8186_mcucfg_regs::reserved69
u32 reserved69[125]
Definition: mcucfg.h:418
mt8186_mcucfg_regs::mp0_dbg_mon
u32 mp0_dbg_mon
Definition: mcucfg.h:34
mt8186_mcucfg_regs::dfd_internal_sram_access
u32 dfd_internal_sram_access
Definition: mcucfg.h:152
mt8186_mcucfg_regs::mcusys_par_wrap_dbg_mon_sel
u32 mcusys_par_wrap_dbg_mon_sel
Definition: mcucfg.h:175
mt8186_mcucfg_regs::mbista_etb_result
u32 mbista_etb_result
Definition: mcucfg.h:21
mt8186_mcucfg_regs::mp0_dcm_cfg8
u32 mp0_dcm_cfg8
Definition: mcucfg.h:459
mt8186_mcucfg_regs::cpu6_resereved_reg
u32 cpu6_resereved_reg
Definition: mcucfg.h:439
mt8186_mcucfg_regs::cci_top_if
u32 cci_top_if
Definition: mcucfg.h:93
mt8186_mcucfg_regs::mp0_cpu1_dc_age
u32 mp0_cpu1_dc_age
Definition: mcucfg.h:111
mt8186_mcucfg_regs::int_msk_ctl4
u32 int_msk_ctl4
Definition: mcucfg.h:284
mt8186_mcucfg_regs::reserved46
u32 reserved46[5]
Definition: mcucfg.h:235
mt8186_mcucfg_regs::cci_tra_cfg5
u32 cci_tra_cfg5
Definition: mcucfg.h:57
mt8186_mcucfg_regs::reserved48
u32 reserved48[15]
Definition: mcucfg.h:239
mt8186_mcucfg_regs::int_pol_ctl10
u32 int_pol_ctl10
Definition: mcucfg.h:270
mt8186_mcucfg_regs::int_msk_ctl_all
u32 int_msk_ctl_all
Definition: mcucfg.h:301
mt8186_mcucfg_regs::int_pol_ctl9
u32 int_pol_ctl9
Definition: mcucfg.h:269
mt8186_mcucfg_regs::plldiv_ctl0
u32 plldiv_ctl0
Definition: mcucfg.h:202
mt8186_mcucfg_regs::cpu3_resereved_reg
u32 cpu3_resereved_reg
Definition: mcucfg.h:427
mt8186_mcucfg_regs::cci_tra_cfg6
u32 cci_tra_cfg6
Definition: mcucfg.h:58
mt8186_mcucfg_regs::cpu_plldiv_cfg0
u32 cpu_plldiv_cfg0
Definition: mcucfg.h:196
mt8186_mcucfg_regs::cci_m2_if
u32 cci_m2_if
Definition: mcucfg.h:86
mt8186_mcucfg_regs::mcusys_on_off_latency
u32 mcusys_on_off_latency
Definition: mcucfg.h:394
mt8186_mcucfg_regs::mcsi_ram_delsel1
u32 mcsi_ram_delsel1
Definition: mcucfg.h:205
mt8186_mcucfg_regs::plldiv_little_reserved
u32 plldiv_little_reserved
Definition: mcucfg.h:511
mt8186_mcucfg_regs::cci_rgu
u32 cci_rgu
Definition: mcucfg.h:211
mt8186_mcucfg_regs::reserved36
u32 reserved36[23]
Definition: mcucfg.h:208
mt8186_mcucfg_regs::cpc_turbo_gp1_resp
u32 cpc_turbo_gp1_resp
Definition: mcucfg.h:343
mt8186_mcucfg_regs::mp0_cluster_cfg13
u32 mp0_cluster_cfg13
Definition: mcucfg.h:477
mt8186_mcucfg_regs::reserved56
u32 reserved56[20]
Definition: mcucfg.h:354
mt8186_mcucfg_regs::mp0_cpu4_dc_age
u32 mp0_cpu4_dc_age
Definition: mcucfg.h:114
mt8186_mcucfg_regs::cci_s3_if
u32 cci_s3_if
Definition: mcucfg.h:90
mt8186_mcucfg_regs::l3c_share_cfg0
u32 l3c_share_cfg0
Definition: mcucfg.h:179
mt8186_mcucfg_regs::mcusys_reserved_reg3_rd
u32 mcusys_reserved_reg3_rd
Definition: mcucfg.h:522
mt8186_mcucfg_regs::mp0_cpu3_nonwfx_ctrl
u32 mp0_cpu3_nonwfx_ctrl
Definition: mcucfg.h:125
mt8186_mcucfg_regs::l2_parity_info2_cpu3
u32 l2_parity_info2_cpu3
Definition: mcucfg.h:44
mt8186_mcucfg_regs::cpc_turbo_gp2_resp
u32 cpc_turbo_gp2_resp
Definition: mcucfg.h:344
mt8186_mcucfg_regs::cpu7_on_off_latency
u32 cpu7_on_off_latency
Definition: mcucfg.h:391
mt8186_mcucfg_regs::mp0_cpu4_nonwfx_cnt
u32 mp0_cpu4_nonwfx_cnt
Definition: mcucfg.h:128
mt8186_mcucfg_regs::int_msk_ctl18
u32 int_msk_ctl18
Definition: mcucfg.h:298
mt8186_mcucfg_regs::pikachu_status
u32 pikachu_status
Definition: mcucfg.h:411
mt8186_mcucfg_regs::mp0_l3_data_ram_delsel
u32 mp0_l3_data_ram_delsel
Definition: mcucfg.h:446
mt8186_mcucfg_regs::cpc_spmc_pwr_status
u32 cpc_spmc_pwr_status
Definition: mcucfg.h:328
mt8186_mcucfg_regs::reserved83
u32 reserved83[174]
Definition: mcucfg.h:490
mt8186_mcucfg_regs::emi_wfifo
u32 emi_wfifo
Definition: mcucfg.h:355
mt8186_mcucfg_regs::mp0_cpu5_nonwfx_cnt
u32 mp0_cpu5_nonwfx_cnt
Definition: mcucfg.h:130
mt8186_mcucfg_regs::cpc_last_core_req
u32 cpc_last_core_req
Definition: mcucfg.h:322
mt8186_mcucfg_regs::mcsic_dcm1
u32 mcsic_dcm1
Definition: mcucfg.h:220
mt8186_mcucfg_regs::reserved82
u32 reserved82[1]
Definition: mcucfg.h:488
mt8186_mcucfg_regs::trace_data_entry0_h
u32 trace_data_entry0_h
Definition: mcucfg.h:377
mt8186_mcucfg_regs::cpu2_drcc_ao_config
u32 cpu2_drcc_ao_config
Definition: mcucfg.h:421
mt8186_mcucfg_regs::mp0_cluster_cfg4
u32 mp0_cluster_cfg4
Definition: mcucfg.h:467
mt8186_mcucfg_regs::gic_periph_base
u32 gic_periph_base
Definition: mcucfg.h:190
mt8186_mcucfg_regs::sec_pol_ctl_en3
u32 sec_pol_ctl_en3
Definition: mcucfg.h:243
mt8186_mcucfg_regs::mp0_cpu5_dc_age
u32 mp0_cpu5_dc_age
Definition: mcucfg.h:115
mt8186_mcucfg_regs::cpu5_resereved_reg
u32 cpu5_resereved_reg
Definition: mcucfg.h:435
mt8186_mcucfg_regs::pikachu_event
u32 pikachu_event
Definition: mcucfg.h:410
mt8186_mcucfg_regs::cpu3_drcc_ao_config
u32 cpu3_drcc_ao_config
Definition: mcucfg.h:425
mt8186_mcucfg_regs::sec_pol_ctl_en13
u32 sec_pol_ctl_en13
Definition: mcucfg.h:253
mt8186_mcucfg_regs::cci_top_if_latch
u32 cci_top_if_latch
Definition: mcucfg.h:104
mt8186_mcucfg_regs::mcsi_cfg4
u32 mcsi_cfg4
Definition: mcucfg.h:217
mt8186_mcucfg_regs::mcusys_par_wrap_dbg_mon
u32 mcusys_par_wrap_dbg_mon
Definition: mcucfg.h:176
mt8186_mcucfg_regs::fcm_spmc_wdt_latch_info
u32 fcm_spmc_wdt_latch_info
Definition: mcucfg.h:310
mt8186_mcucfg_regs::l2_parity_info2_cpu6
u32 l2_parity_info2_cpu6
Definition: mcucfg.h:50
mt8186_mcucfg_regs::reserved89
u32 reserved89[3183]
Definition: mcucfg.h:514
mt8186_mcucfg_regs::cpu5_drcc_ao_config
u32 cpu5_drcc_ao_config
Definition: mcucfg.h:433
mt8186_mcucfg_regs::dfd_internal_pwr_on
u32 dfd_internal_pwr_on
Definition: mcucfg.h:148
mt8186_mcucfg_regs::mp0_dbg_mon_sel
u32 mp0_dbg_mon_sel
Definition: mcucfg.h:33
mt8186_mcucfg_regs::mp0_cluster_cfg21
u32 mp0_cluster_cfg21
Definition: mcucfg.h:485
mt8186_mcucfg_regs::cci_tra_cfg9
u32 cci_tra_cfg9
Definition: mcucfg.h:61
mt8186_mcucfg_regs::reserved21
u32 reserved21[48]
Definition: mcucfg.h:135
mt8186_mcucfg_regs::reserved61
u32 reserved61[29]
Definition: mcucfg.h:368
mt8186_mcucfg_regs::cci_m0_tra_latch
u32 cci_m0_tra_latch
Definition: mcucfg.h:75
mt8186_mcucfg_regs::cci_m2_tra_latch
u32 cci_m2_tra_latch
Definition: mcucfg.h:77
mt8186_mcucfg_regs::mp0_cpu2_nonwfx_ctrl
u32 mp0_cpu2_nonwfx_ctrl
Definition: mcucfg.h:123
mt8186_mcucfg_regs::int_msk_ctl13
u32 int_msk_ctl13
Definition: mcucfg.h:293
mt8186_mcucfg_regs::sec_pol_ctl_en19
u32 sec_pol_ctl_en19
Definition: mcucfg.h:259
mt8186_mcucfg_regs::mcusys_spmc_sw_cfg
u32 mcusys_spmc_sw_cfg
Definition: mcucfg.h:312
mt8186_mcucfg_regs::cpu7_drcc_ao_config
u32 cpu7_drcc_ao_config
Definition: mcucfg.h:441
mt8186_mcucfg_regs::int_pol_ctl16
u32 int_pol_ctl16
Definition: mcucfg.h:276
mt8186_mcucfg_regs::reserved81
u32 reserved81[4]
Definition: mcucfg.h:471
mt8186_mcucfg_regs::mp_top_dbg_mon
u32 mp_top_dbg_mon
Definition: mcucfg.h:32
mt8186_mcucfg_regs::cpu1_resereved_reg
u32 cpu1_resereved_reg
Definition: mcucfg.h:419
mt8186_mcucfg_regs::int_msk_ctl9
u32 int_msk_ctl9
Definition: mcucfg.h:289
mt8186_mcucfg_regs::cci_m1_tra_latch
u32 cci_m1_tra_latch
Definition: mcucfg.h:76
mt8186_mcucfg_regs::dfd_internal_test_so_over_64
u32 dfd_internal_test_so_over_64
Definition: mcucfg.h:159
mt8186_mcucfg_regs::mp0_cluster_cfg15
u32 mp0_cluster_cfg15
Definition: mcucfg.h:479
mt8186_mcucfg_regs::reserved29
u32 reserved29[2]
Definition: mcucfg.h:185
mt8186_mcucfg_regs::int_pol_ctl8
u32 int_pol_ctl8
Definition: mcucfg.h:268
mt8186_mcucfg_regs::mp0_cluster_cfg5
u32 mp0_cluster_cfg5
Definition: mcucfg.h:468
mt8186_mcucfg_regs::reserved47
u32 reserved47[7]
Definition: mcucfg.h:237
mt8186_mcucfg_regs::cci_s2_if
u32 cci_s2_if
Definition: mcucfg.h:89
mt8186_mcucfg_regs::dfd_ctrl
u32 dfd_ctrl
Definition: mcucfg.h:27
mt8186_mcucfg_regs::int_pol_ctl2
u32 int_pol_ctl2
Definition: mcucfg.h:262
mt8186_mcucfg_regs::cci_m2_tra
u32 cci_m2_tra
Definition: mcucfg.h:68
mt8186_mcucfg_regs::mp0_cpu6_nonwfx_ctrl
u32 mp0_cpu6_nonwfx_ctrl
Definition: mcucfg.h:131
mt8186_mcucfg_regs::mp0_dcm_cfg3
u32 mp0_dcm_cfg3
Definition: mcucfg.h:454
mt8186_mcucfg_regs::reserved35
u32 reserved35[6]
Definition: mcucfg.h:206
mt8186_mcucfg_regs::l2_parity_info2_cpu4
u32 l2_parity_info2_cpu4
Definition: mcucfg.h:46
mt8186_mcucfg_regs::reserved76
u32 reserved76[528]
Definition: mcucfg.h:445
mt8186_mcucfg_regs::cpu4_drcc_ao_config
u32 cpu4_drcc_ao_config
Definition: mcucfg.h:429
mt8186_mcucfg_regs::dfd_internal_test_so_0
u32 dfd_internal_test_so_0
Definition: mcucfg.h:156
mt8186_mcucfg_regs::l2_parity_info2_cpu5
u32 l2_parity_info2_cpu5
Definition: mcucfg.h:48
mt8186_mcucfg_regs::fcm_spmc_wait_cfg
u32 fcm_spmc_wait_cfg
Definition: mcucfg.h:306
mt8186_mcucfg_regs::reserved1
u32 reserved1[2]
Definition: mcucfg.h:15
mt8186_mcucfg_regs::l3c_sram_base
u32 l3c_sram_base
Definition: mcucfg.h:189
mt8186_mcucfg_regs::mcusys_reserved_reg2_rd
u32 mcusys_reserved_reg2_rd
Definition: mcucfg.h:521
mt8186_mcucfg_regs::l2_parity_info2_cpu1
u32 l2_parity_info2_cpu1
Definition: mcucfg.h:40
mt8186_mcucfg_regs::int_pol_ctl19
u32 int_pol_ctl19
Definition: mcucfg.h:279
mt8186_mcucfg_regs::mp0_cpu3_nonwfx_cnt
u32 mp0_cpu3_nonwfx_cnt
Definition: mcucfg.h:126
mt8186_mcucfg_regs::reserved33
u32 reserved33[3]
Definition: mcucfg.h:201
mt8186_mcucfg_regs::cpu_type1_ram_delsel1_cfg
u32 cpu_type1_ram_delsel1_cfg
Definition: mcucfg.h:502