#include <mcucfg.h>
Definition at line 14 of file mcucfg.h.
◆ adb_bist_cfg1
| u32 mt8186_mcucfg_regs::adb_bist_cfg1 |
◆ adb_bist_cfg2_md
| u32 mt8186_mcucfg_regs::adb_bist_cfg2_md |
◆ adb_bist_cfg3_go
| u32 mt8186_mcucfg_regs::adb_bist_cfg3_go |
◆ adb_bist_done
| u32 mt8186_mcucfg_regs::adb_bist_done |
◆ adb_bist_pass
| u32 mt8186_mcucfg_regs::adb_bist_pass |
◆ apmcu2emi_early_cke_ctl
| u32 mt8186_mcucfg_regs::apmcu2emi_early_cke_ctl |
◆ axi1to4_cfg
| u32 mt8186_mcucfg_regs::axi1to4_cfg |
◆ bus_plldiv_cfg
| u32 mt8186_mcucfg_regs::bus_plldiv_cfg |
◆ cci_m0_if
| u32 mt8186_mcucfg_regs::cci_m0_if |
◆ cci_m0_if_latch
| u32 mt8186_mcucfg_regs::cci_m0_if_latch |
◆ cci_m0_tra
| u32 mt8186_mcucfg_regs::cci_m0_tra |
◆ cci_m0_tra_latch
| u32 mt8186_mcucfg_regs::cci_m0_tra_latch |
◆ cci_m1_if
| u32 mt8186_mcucfg_regs::cci_m1_if |
◆ cci_m1_if_latch
| u32 mt8186_mcucfg_regs::cci_m1_if_latch |
◆ cci_m1_tra
| u32 mt8186_mcucfg_regs::cci_m1_tra |
◆ cci_m1_tra_latch
| u32 mt8186_mcucfg_regs::cci_m1_tra_latch |
◆ cci_m2_if
| u32 mt8186_mcucfg_regs::cci_m2_if |
◆ cci_m2_if_latch
| u32 mt8186_mcucfg_regs::cci_m2_if_latch |
◆ cci_m2_tra
| u32 mt8186_mcucfg_regs::cci_m2_tra |
◆ cci_m2_tra_latch
| u32 mt8186_mcucfg_regs::cci_m2_tra_latch |
◆ cci_periph_base
| u32 mt8186_mcucfg_regs::cci_periph_base |
◆ cci_periph_infra_base
| u32 mt8186_mcucfg_regs::cci_periph_infra_base |
◆ cci_rgu
| u32 mt8186_mcucfg_regs::cci_rgu |
◆ cci_s1_if
| u32 mt8186_mcucfg_regs::cci_s1_if |
◆ cci_s1_if_latch
| u32 mt8186_mcucfg_regs::cci_s1_if_latch |
◆ cci_s1_tra
| u32 mt8186_mcucfg_regs::cci_s1_tra |
◆ cci_s1_tra_latch
| u32 mt8186_mcucfg_regs::cci_s1_tra_latch |
◆ cci_s2_if
| u32 mt8186_mcucfg_regs::cci_s2_if |
◆ cci_s2_if_latch
| u32 mt8186_mcucfg_regs::cci_s2_if_latch |
◆ cci_s2_tra
| u32 mt8186_mcucfg_regs::cci_s2_tra |
◆ cci_s2_tra_latch
| u32 mt8186_mcucfg_regs::cci_s2_tra_latch |
◆ cci_s3_if
| u32 mt8186_mcucfg_regs::cci_s3_if |
◆ cci_s3_if_latch
| u32 mt8186_mcucfg_regs::cci_s3_if_latch |
◆ cci_s3_tra
| u32 mt8186_mcucfg_regs::cci_s3_tra |
◆ cci_s3_tra_latch
| u32 mt8186_mcucfg_regs::cci_s3_tra_latch |
◆ cci_s4_if
| u32 mt8186_mcucfg_regs::cci_s4_if |
◆ cci_s4_if_latch
| u32 mt8186_mcucfg_regs::cci_s4_if_latch |
◆ cci_s4_tra
| u32 mt8186_mcucfg_regs::cci_s4_tra |
◆ cci_s4_tra_latch
| u32 mt8186_mcucfg_regs::cci_s4_tra_latch |
◆ cci_top_if
| u32 mt8186_mcucfg_regs::cci_top_if |
◆ cci_top_if_latch
| u32 mt8186_mcucfg_regs::cci_top_if_latch |
◆ cci_tra_cfg0
| u32 mt8186_mcucfg_regs::cci_tra_cfg0 |
◆ cci_tra_cfg10
| u32 mt8186_mcucfg_regs::cci_tra_cfg10 |
◆ cci_tra_cfg11
| u32 mt8186_mcucfg_regs::cci_tra_cfg11 |
◆ cci_tra_cfg12
| u32 mt8186_mcucfg_regs::cci_tra_cfg12 |
◆ cci_tra_cfg5
| u32 mt8186_mcucfg_regs::cci_tra_cfg5 |
◆ cci_tra_cfg6
| u32 mt8186_mcucfg_regs::cci_tra_cfg6 |
◆ cci_tra_cfg7
| u32 mt8186_mcucfg_regs::cci_tra_cfg7 |
◆ cci_tra_cfg8
| u32 mt8186_mcucfg_regs::cci_tra_cfg8 |
◆ cci_tra_cfg9
| u32 mt8186_mcucfg_regs::cci_tra_cfg9 |
◆ cluster_off_dormant_counter
| u32 mt8186_mcucfg_regs::cluster_off_dormant_counter |
◆ cluster_off_dormant_counter_clear
| u32 mt8186_mcucfg_regs::cluster_off_dormant_counter_clear |
◆ cluster_off_latency
| u32 mt8186_mcucfg_regs::cluster_off_latency |
◆ cluster_on_latency
| u32 mt8186_mcucfg_regs::cluster_on_latency |
◆ cpc_coh_block_thres
| u32 mt8186_mcucfg_regs::cpc_coh_block_thres |
◆ cpc_core_cur_fsm
| u32 mt8186_mcucfg_regs::cpc_core_cur_fsm |
◆ cpc_cpu_on_sw_hint
| u32 mt8186_mcucfg_regs::cpc_cpu_on_sw_hint |
◆ cpc_cpu_on_sw_hint_clear
| u32 mt8186_mcucfg_regs::cpc_cpu_on_sw_hint_clear |
◆ cpc_cpu_on_sw_hint_set
| u32 mt8186_mcucfg_regs::cpc_cpu_on_sw_hint_set |
◆ cpc_cpusys_last_core_resp
| u32 mt8186_mcucfg_regs::cpc_cpusys_last_core_resp |
◆ cpc_cpusys_mcusys_cur_fsm
| u32 mt8186_mcucfg_regs::cpc_cpusys_mcusys_cur_fsm |
◆ cpc_dcm_enable
| u32 mt8186_mcucfg_regs::cpc_dcm_enable |
◆ cpc_flow_ctrl_cfg
| u32 mt8186_mcucfg_regs::cpc_flow_ctrl_cfg |
◆ cpc_int_enable
| u32 mt8186_mcucfg_regs::cpc_int_enable |
◆ cpc_int_status
| u32 mt8186_mcucfg_regs::cpc_int_status |
◆ cpc_last_core_req
| u32 mt8186_mcucfg_regs::cpc_last_core_req |
◆ cpc_mcusys_last_core_resp
| u32 mt8186_mcucfg_regs::cpc_mcusys_last_core_resp |
◆ cpc_pllbuck_arb_weight
| u32 mt8186_mcucfg_regs::cpc_pllbuck_arb_weight |
◆ cpc_pllbuck_req_ctrl
| u32 mt8186_mcucfg_regs::cpc_pllbuck_req_ctrl |
◆ cpc_pllbuck_state
| u32 mt8186_mcucfg_regs::cpc_pllbuck_state |
◆ cpc_pmu_cnt0
| u32 mt8186_mcucfg_regs::cpc_pmu_cnt0 |
◆ cpc_pmu_cnt_clr
| u32 mt8186_mcucfg_regs::cpc_pmu_cnt_clr |
◆ cpc_pmu_ctrl
| u32 mt8186_mcucfg_regs::cpc_pmu_ctrl |
◆ cpc_pwr_on_mask
| u32 mt8186_mcucfg_regs::cpc_pwr_on_mask |
◆ cpc_spmc_pwr_status
| u32 mt8186_mcucfg_regs::cpc_spmc_pwr_status |
◆ cpc_turbo_ctrl
| u32 mt8186_mcucfg_regs::cpc_turbo_ctrl |
◆ cpc_turbo_gp0_ctrl
| u32 mt8186_mcucfg_regs::cpc_turbo_gp0_ctrl |
◆ cpc_turbo_gp0_req
| u32 mt8186_mcucfg_regs::cpc_turbo_gp0_req |
◆ cpc_turbo_gp0_resp
| u32 mt8186_mcucfg_regs::cpc_turbo_gp0_resp |
◆ cpc_turbo_gp1_ctrl
| u32 mt8186_mcucfg_regs::cpc_turbo_gp1_ctrl |
◆ cpc_turbo_gp1_req
| u32 mt8186_mcucfg_regs::cpc_turbo_gp1_req |
◆ cpc_turbo_gp1_resp
| u32 mt8186_mcucfg_regs::cpc_turbo_gp1_resp |
◆ cpc_turbo_gp2_ctrl
| u32 mt8186_mcucfg_regs::cpc_turbo_gp2_ctrl |
◆ cpc_turbo_gp2_req
| u32 mt8186_mcucfg_regs::cpc_turbo_gp2_req |
◆ cpc_turbo_gp2_resp
| u32 mt8186_mcucfg_regs::cpc_turbo_gp2_resp |
◆ cpc_turbo_pwr_on_mask
| u32 mt8186_mcucfg_regs::cpc_turbo_pwr_on_mask |
◆ cpc_wakeup_req
| u32 mt8186_mcucfg_regs::cpc_wakeup_req |
◆ cpc_wdt_latch_info1
| u32 mt8186_mcucfg_regs::cpc_wdt_latch_info1 |
◆ cpc_wdt_latch_info2
| u32 mt8186_mcucfg_regs::cpc_wdt_latch_info2 |
◆ cpc_wdt_latch_info3
| u32 mt8186_mcucfg_regs::cpc_wdt_latch_info3 |
◆ cpc_wdt_latch_info4
| u32 mt8186_mcucfg_regs::cpc_wdt_latch_info4 |
◆ cpc_wdt_latch_info5
| u32 mt8186_mcucfg_regs::cpc_wdt_latch_info5 |
◆ cpu0_drcc_ao_config
| u32 mt8186_mcucfg_regs::cpu0_drcc_ao_config |
◆ cpu0_on_off_latency
| u32 mt8186_mcucfg_regs::cpu0_on_off_latency |
◆ cpu0_resereved_reg
| u32 mt8186_mcucfg_regs::cpu0_resereved_reg |
◆ cpu0_resereved_reg_rd
| u32 mt8186_mcucfg_regs::cpu0_resereved_reg_rd |
◆ cpu1_drcc_ao_config
| u32 mt8186_mcucfg_regs::cpu1_drcc_ao_config |
◆ cpu1_on_off_latency
| u32 mt8186_mcucfg_regs::cpu1_on_off_latency |
◆ cpu1_resereved_reg
| u32 mt8186_mcucfg_regs::cpu1_resereved_reg |
◆ cpu1_resereved_reg_rd
| u32 mt8186_mcucfg_regs::cpu1_resereved_reg_rd |
◆ cpu2_drcc_ao_config
| u32 mt8186_mcucfg_regs::cpu2_drcc_ao_config |
◆ cpu2_on_off_latency
| u32 mt8186_mcucfg_regs::cpu2_on_off_latency |
◆ cpu2_resereved_reg
| u32 mt8186_mcucfg_regs::cpu2_resereved_reg |
◆ cpu2_resereved_reg_rd
| u32 mt8186_mcucfg_regs::cpu2_resereved_reg_rd |
◆ cpu3_drcc_ao_config
| u32 mt8186_mcucfg_regs::cpu3_drcc_ao_config |
◆ cpu3_on_off_latency
| u32 mt8186_mcucfg_regs::cpu3_on_off_latency |
◆ cpu3_resereved_reg
| u32 mt8186_mcucfg_regs::cpu3_resereved_reg |
◆ cpu3_resereved_reg_rd
| u32 mt8186_mcucfg_regs::cpu3_resereved_reg_rd |
◆ cpu4_drcc_ao_config
| u32 mt8186_mcucfg_regs::cpu4_drcc_ao_config |
◆ cpu4_on_off_latency
| u32 mt8186_mcucfg_regs::cpu4_on_off_latency |
◆ cpu4_resereved_reg
| u32 mt8186_mcucfg_regs::cpu4_resereved_reg |
◆ cpu4_resereved_reg_rd
| u32 mt8186_mcucfg_regs::cpu4_resereved_reg_rd |
◆ cpu5_drcc_ao_config
| u32 mt8186_mcucfg_regs::cpu5_drcc_ao_config |
◆ cpu5_on_off_latency
| u32 mt8186_mcucfg_regs::cpu5_on_off_latency |
◆ cpu5_resereved_reg
| u32 mt8186_mcucfg_regs::cpu5_resereved_reg |
◆ cpu5_resereved_reg_rd
| u32 mt8186_mcucfg_regs::cpu5_resereved_reg_rd |
◆ cpu6_drcc_ao_config
| u32 mt8186_mcucfg_regs::cpu6_drcc_ao_config |
◆ cpu6_on_off_latency
| u32 mt8186_mcucfg_regs::cpu6_on_off_latency |
◆ cpu6_resereved_reg
| u32 mt8186_mcucfg_regs::cpu6_resereved_reg |
◆ cpu6_resereved_reg_rd
| u32 mt8186_mcucfg_regs::cpu6_resereved_reg_rd |
◆ cpu7_drcc_ao_config
| u32 mt8186_mcucfg_regs::cpu7_drcc_ao_config |
◆ cpu7_on_off_latency
| u32 mt8186_mcucfg_regs::cpu7_on_off_latency |
◆ cpu7_resereved_reg
| u32 mt8186_mcucfg_regs::cpu7_resereved_reg |
◆ cpu7_resereved_reg_rd
| u32 mt8186_mcucfg_regs::cpu7_resereved_reg_rd |
◆ cpu_plldiv_cfg0
| u32 mt8186_mcucfg_regs::cpu_plldiv_cfg0 |
◆ cpu_plldiv_cfg1
| u32 mt8186_mcucfg_regs::cpu_plldiv_cfg1 |
◆ cpu_plldiv_cfg2
| u32 mt8186_mcucfg_regs::cpu_plldiv_cfg2 |
◆ cpu_type0_ram_delsel0_cfg
| u32 mt8186_mcucfg_regs::cpu_type0_ram_delsel0_cfg |
◆ cpu_type0_ram_delsel1_cfg
| u32 mt8186_mcucfg_regs::cpu_type0_ram_delsel1_cfg |
◆ cpu_type0_ram_delsel2_cfg
| u32 mt8186_mcucfg_regs::cpu_type0_ram_delsel2_cfg |
◆ cpu_type0_spmc0_cfg
| u32 mt8186_mcucfg_regs::cpu_type0_spmc0_cfg |
◆ cpu_type1_mpmmen
| u32 mt8186_mcucfg_regs::cpu_type1_mpmmen |
◆ cpu_type1_ram_delsel0_cfg
| u32 mt8186_mcucfg_regs::cpu_type1_ram_delsel0_cfg |
◆ cpu_type1_ram_delsel1_cfg
| u32 mt8186_mcucfg_regs::cpu_type1_ram_delsel1_cfg |
◆ cpu_type1_ram_delsel2_cfg
| u32 mt8186_mcucfg_regs::cpu_type1_ram_delsel2_cfg |
◆ cpu_type1_spmc0_cfg
| u32 mt8186_mcucfg_regs::cpu_type1_spmc0_cfg |
◆ cpusys_pwr_ctrl
| u32 mt8186_mcucfg_regs::cpusys_pwr_ctrl |
◆ dcc_bus_con0
| u32 mt8186_mcucfg_regs::dcc_bus_con0 |
◆ dcc_cpu_con0
| u32 mt8186_mcucfg_regs::dcc_cpu_con0 |
◆ dcc_cpu_con1
| u32 mt8186_mcucfg_regs::dcc_cpu_con1 |
◆ dcc_cpu_con2
| u32 mt8186_mcucfg_regs::dcc_cpu_con2 |
◆ dfd_cnt_h
| u32 mt8186_mcucfg_regs::dfd_cnt_h |
◆ dfd_cnt_l
| u32 mt8186_mcucfg_regs::dfd_cnt_l |
◆ dfd_ctrl
| u32 mt8186_mcucfg_regs::dfd_ctrl |
◆ dfd_hw_trigger_mask
| u32 mt8186_mcucfg_regs::dfd_hw_trigger_mask |
◆ dfd_internal_chain_legth_0
| u32 mt8186_mcucfg_regs::dfd_internal_chain_legth_0 |
◆ dfd_internal_chain_length_1
| u32 mt8186_mcucfg_regs::dfd_internal_chain_length_1 |
◆ dfd_internal_chain_length_2
| u32 mt8186_mcucfg_regs::dfd_internal_chain_length_2 |
◆ dfd_internal_chain_length_3
| u32 mt8186_mcucfg_regs::dfd_internal_chain_length_3 |
◆ dfd_internal_counter
| u32 mt8186_mcucfg_regs::dfd_internal_counter |
◆ dfd_internal_counter_return
| u32 mt8186_mcucfg_regs::dfd_internal_counter_return |
◆ dfd_internal_ctl
| u32 mt8186_mcucfg_regs::dfd_internal_ctl |
◆ dfd_internal_mask_out
| u32 mt8186_mcucfg_regs::dfd_internal_mask_out |
◆ dfd_internal_mcsi
| u32 mt8186_mcucfg_regs::dfd_internal_mcsi |
◆ dfd_internal_mcsi_sel_status
| u32 mt8186_mcucfg_regs::dfd_internal_mcsi_sel_status |
◆ dfd_internal_num_of_test_so_gp
| u32 mt8186_mcucfg_regs::dfd_internal_num_of_test_so_gp |
◆ dfd_internal_pwr_on
| u32 mt8186_mcucfg_regs::dfd_internal_pwr_on |
◆ dfd_internal_shift_clk_ratio
| u32 mt8186_mcucfg_regs::dfd_internal_shift_clk_ratio |
◆ dfd_internal_sram_access
| u32 mt8186_mcucfg_regs::dfd_internal_sram_access |
◆ dfd_internal_sw_ns_trigger
| u32 mt8186_mcucfg_regs::dfd_internal_sw_ns_trigger |
◆ dfd_internal_test_so_0
| u32 mt8186_mcucfg_regs::dfd_internal_test_so_0 |
◆ dfd_internal_test_so_1
| u32 mt8186_mcucfg_regs::dfd_internal_test_so_1 |
◆ dfd_internal_test_so_over_64
| u32 mt8186_mcucfg_regs::dfd_internal_test_so_over_64 |
◆ dfd_power_ctl
| u32 mt8186_mcucfg_regs::dfd_power_ctl |
◆ dfd_reset_on
| u32 mt8186_mcucfg_regs::dfd_reset_on |
◆ dfd_sram_base
| u32 mt8186_mcucfg_regs::dfd_sram_base |
◆ dfd_status_clean
| u32 mt8186_mcucfg_regs::dfd_status_clean |
◆ dfd_status_return
| u32 mt8186_mcucfg_regs::dfd_status_return |
◆ dfd_test_si_0
| u32 mt8186_mcucfg_regs::dfd_test_si_0 |
◆ dfd_test_si_1
| u32 mt8186_mcucfg_regs::dfd_test_si_1 |
◆ dfd_v30_base_addr
| u32 mt8186_mcucfg_regs::dfd_v30_base_addr |
◆ dfd_v30_ctl
| u32 mt8186_mcucfg_regs::dfd_v30_ctl |
◆ emi_adb_edge_sel
| u32 mt8186_mcucfg_regs::emi_adb_edge_sel |
◆ emi_wfifo
| u32 mt8186_mcucfg_regs::emi_wfifo |
◆ etb_cfg0
| u32 mt8186_mcucfg_regs::etb_cfg0 |
◆ etb_ck_ctl
| u32 mt8186_mcucfg_regs::etb_ck_ctl |
◆ etb_ram_delsel0
| u32 mt8186_mcucfg_regs::etb_ram_delsel0 |
◆ fcm_spmc_off_thres
| u32 mt8186_mcucfg_regs::fcm_spmc_off_thres |
◆ fcm_spmc_pwr_status
| u32 mt8186_mcucfg_regs::fcm_spmc_pwr_status |
◆ fcm_spmc_sw_cfg1
| u32 mt8186_mcucfg_regs::fcm_spmc_sw_cfg1 |
◆ fcm_spmc_sw_cfg2
| u32 mt8186_mcucfg_regs::fcm_spmc_sw_cfg2 |
◆ fcm_spmc_sw_pchannel
| u32 mt8186_mcucfg_regs::fcm_spmc_sw_pchannel |
◆ fcm_spmc_wait_cfg
| u32 mt8186_mcucfg_regs::fcm_spmc_wait_cfg |
◆ fcm_spmc_wdt_latch_info
| u32 mt8186_mcucfg_regs::fcm_spmc_wdt_latch_info |
◆ gic_acao_ctl0
| u32 mt8186_mcucfg_regs::gic_acao_ctl0 |
◆ gic_acao_ctl1
| u32 mt8186_mcucfg_regs::gic_acao_ctl1 |
◆ gic_acao_ctl2
| u32 mt8186_mcucfg_regs::gic_acao_ctl2 |
◆ gic_periph_base
| u32 mt8186_mcucfg_regs::gic_periph_base |
◆ ildo_vproc2_en
| u32 mt8186_mcucfg_regs::ildo_vproc2_en |
◆ int_cfg_direct_access_en
| u32 mt8186_mcucfg_regs::int_cfg_direct_access_en |
◆ int_cfg_indirect_access
| u32 mt8186_mcucfg_regs::int_cfg_indirect_access |
◆ int_msk_ctl0
| u32 mt8186_mcucfg_regs::int_msk_ctl0 |
◆ int_msk_ctl1
| u32 mt8186_mcucfg_regs::int_msk_ctl1 |
◆ int_msk_ctl10
| u32 mt8186_mcucfg_regs::int_msk_ctl10 |
◆ int_msk_ctl11
| u32 mt8186_mcucfg_regs::int_msk_ctl11 |
◆ int_msk_ctl12
| u32 mt8186_mcucfg_regs::int_msk_ctl12 |
◆ int_msk_ctl13
| u32 mt8186_mcucfg_regs::int_msk_ctl13 |
◆ int_msk_ctl14
| u32 mt8186_mcucfg_regs::int_msk_ctl14 |
◆ int_msk_ctl15
| u32 mt8186_mcucfg_regs::int_msk_ctl15 |
◆ int_msk_ctl16
| u32 mt8186_mcucfg_regs::int_msk_ctl16 |
◆ int_msk_ctl17
| u32 mt8186_mcucfg_regs::int_msk_ctl17 |
◆ int_msk_ctl18
| u32 mt8186_mcucfg_regs::int_msk_ctl18 |
◆ int_msk_ctl19
| u32 mt8186_mcucfg_regs::int_msk_ctl19 |
◆ int_msk_ctl2
| u32 mt8186_mcucfg_regs::int_msk_ctl2 |
◆ int_msk_ctl3
| u32 mt8186_mcucfg_regs::int_msk_ctl3 |
◆ int_msk_ctl4
| u32 mt8186_mcucfg_regs::int_msk_ctl4 |
◆ int_msk_ctl5
| u32 mt8186_mcucfg_regs::int_msk_ctl5 |
◆ int_msk_ctl6
| u32 mt8186_mcucfg_regs::int_msk_ctl6 |
◆ int_msk_ctl7
| u32 mt8186_mcucfg_regs::int_msk_ctl7 |
◆ int_msk_ctl8
| u32 mt8186_mcucfg_regs::int_msk_ctl8 |
◆ int_msk_ctl9
| u32 mt8186_mcucfg_regs::int_msk_ctl9 |
◆ int_msk_ctl_all
| u32 mt8186_mcucfg_regs::int_msk_ctl_all |
◆ int_pol_ctl0
| u32 mt8186_mcucfg_regs::int_pol_ctl0 |
◆ int_pol_ctl1
| u32 mt8186_mcucfg_regs::int_pol_ctl1 |
◆ int_pol_ctl10
| u32 mt8186_mcucfg_regs::int_pol_ctl10 |
◆ int_pol_ctl11
| u32 mt8186_mcucfg_regs::int_pol_ctl11 |
◆ int_pol_ctl12
| u32 mt8186_mcucfg_regs::int_pol_ctl12 |
◆ int_pol_ctl13
| u32 mt8186_mcucfg_regs::int_pol_ctl13 |
◆ int_pol_ctl14
| u32 mt8186_mcucfg_regs::int_pol_ctl14 |
◆ int_pol_ctl15
| u32 mt8186_mcucfg_regs::int_pol_ctl15 |
◆ int_pol_ctl16
| u32 mt8186_mcucfg_regs::int_pol_ctl16 |
◆ int_pol_ctl17
| u32 mt8186_mcucfg_regs::int_pol_ctl17 |
◆ int_pol_ctl18
| u32 mt8186_mcucfg_regs::int_pol_ctl18 |
◆ int_pol_ctl19
| u32 mt8186_mcucfg_regs::int_pol_ctl19 |
◆ int_pol_ctl2
| u32 mt8186_mcucfg_regs::int_pol_ctl2 |
◆ int_pol_ctl3
| u32 mt8186_mcucfg_regs::int_pol_ctl3 |
◆ int_pol_ctl4
| u32 mt8186_mcucfg_regs::int_pol_ctl4 |
◆ int_pol_ctl5
| u32 mt8186_mcucfg_regs::int_pol_ctl5 |
◆ int_pol_ctl6
| u32 mt8186_mcucfg_regs::int_pol_ctl6 |
◆ int_pol_ctl7
| u32 mt8186_mcucfg_regs::int_pol_ctl7 |
◆ int_pol_ctl8
| u32 mt8186_mcucfg_regs::int_pol_ctl8 |
◆ int_pol_ctl9
| u32 mt8186_mcucfg_regs::int_pol_ctl9 |
◆ kernel_base_h
| u32 mt8186_mcucfg_regs::kernel_base_h |
◆ kernel_base_l
| u32 mt8186_mcucfg_regs::kernel_base_l |
◆ l2_parity_clr
| u32 mt8186_mcucfg_regs::l2_parity_clr |
◆ l2_parity_info1_cpu0
| u32 mt8186_mcucfg_regs::l2_parity_info1_cpu0 |
◆ l2_parity_info1_cpu1
| u32 mt8186_mcucfg_regs::l2_parity_info1_cpu1 |
◆ l2_parity_info1_cpu2
| u32 mt8186_mcucfg_regs::l2_parity_info1_cpu2 |
◆ l2_parity_info1_cpu3
| u32 mt8186_mcucfg_regs::l2_parity_info1_cpu3 |
◆ l2_parity_info1_cpu4
| u32 mt8186_mcucfg_regs::l2_parity_info1_cpu4 |
◆ l2_parity_info1_cpu5
| u32 mt8186_mcucfg_regs::l2_parity_info1_cpu5 |
◆ l2_parity_info1_cpu6
| u32 mt8186_mcucfg_regs::l2_parity_info1_cpu6 |
◆ l2_parity_info1_cpu7
| u32 mt8186_mcucfg_regs::l2_parity_info1_cpu7 |
◆ l2_parity_info2_cpu0
| u32 mt8186_mcucfg_regs::l2_parity_info2_cpu0 |
◆ l2_parity_info2_cpu1
| u32 mt8186_mcucfg_regs::l2_parity_info2_cpu1 |
◆ l2_parity_info2_cpu2
| u32 mt8186_mcucfg_regs::l2_parity_info2_cpu2 |
◆ l2_parity_info2_cpu3
| u32 mt8186_mcucfg_regs::l2_parity_info2_cpu3 |
◆ l2_parity_info2_cpu4
| u32 mt8186_mcucfg_regs::l2_parity_info2_cpu4 |
◆ l2_parity_info2_cpu5
| u32 mt8186_mcucfg_regs::l2_parity_info2_cpu5 |
◆ l2_parity_info2_cpu6
| u32 mt8186_mcucfg_regs::l2_parity_info2_cpu6 |
◆ l2_parity_info2_cpu7
| u32 mt8186_mcucfg_regs::l2_parity_info2_cpu7 |
◆ l3c_mm_sram_base
| u32 mt8186_mcucfg_regs::l3c_mm_sram_base |
◆ l3c_share_cfg0
| u32 mt8186_mcucfg_regs::l3c_share_cfg0 |
◆ l3c_share_cfg1
| u32 mt8186_mcucfg_regs::l3c_share_cfg1 |
◆ l3c_share_cfg2
| u32 mt8186_mcucfg_regs::l3c_share_cfg2 |
◆ l3c_share_status0
| u32 mt8186_mcucfg_regs::l3c_share_status0 |
◆ l3c_share_status1
| u32 mt8186_mcucfg_regs::l3c_share_status1 |
◆ l3c_share_status2
| u32 mt8186_mcucfg_regs::l3c_share_status2 |
◆ l3c_sram_base
| u32 mt8186_mcucfg_regs::l3c_sram_base |
◆ mbist_trigger_mux_ctl
| u32 mt8186_mcucfg_regs::mbist_trigger_mux_ctl |
◆ mbista_all_result
| u32 mt8186_mcucfg_regs::mbista_all_result |
◆ mbista_etb_con
| u32 mt8186_mcucfg_regs::mbista_etb_con |
◆ mbista_etb_result
| u32 mt8186_mcucfg_regs::mbista_etb_result |
◆ mbista_mcsi_sf1_con
| u32 mt8186_mcucfg_regs::mbista_mcsi_sf1_con |
◆ mbista_mcsi_sf1_result
| u32 mt8186_mcucfg_regs::mbista_mcsi_sf1_result |
◆ mbista_mcsi_sf2_con
| u32 mt8186_mcucfg_regs::mbista_mcsi_sf2_con |
◆ mbista_mcsi_sf2_result
| u32 mt8186_mcucfg_regs::mbista_mcsi_sf2_result |
◆ mbista_rstb
| u32 mt8186_mcucfg_regs::mbista_rstb |
◆ mcsi_cfg0
| u32 mt8186_mcucfg_regs::mcsi_cfg0 |
◆ mcsi_cfg1
| u32 mt8186_mcucfg_regs::mcsi_cfg1 |
◆ mcsi_cfg2
| u32 mt8186_mcucfg_regs::mcsi_cfg2 |
◆ mcsi_cfg3
| u32 mt8186_mcucfg_regs::mcsi_cfg3 |
◆ mcsi_cfg4
| u32 mt8186_mcucfg_regs::mcsi_cfg4 |
◆ mcsi_ram_delsel0
| u32 mt8186_mcucfg_regs::mcsi_ram_delsel0 |
◆ mcsi_ram_delsel1
| u32 mt8186_mcucfg_regs::mcsi_ram_delsel1 |
◆ mcsic_dcm0
| u32 mt8186_mcucfg_regs::mcsic_dcm0 |
◆ mcsic_dcm1
| u32 mt8186_mcucfg_regs::mcsic_dcm1 |
◆ mcusys_base
| u32 mt8186_mcucfg_regs::mcusys_base |
◆ mcusys_core_status
| u32 mt8186_mcucfg_regs::mcusys_core_status |
◆ mcusys_dbg_mon
| u32 mt8186_mcucfg_regs::mcusys_dbg_mon |
◆ mcusys_dbg_mon_sel
| u32 mt8186_mcucfg_regs::mcusys_dbg_mon_sel |
◆ mcusys_dcm_cfg0
| u32 mt8186_mcucfg_regs::mcusys_dcm_cfg0 |
◆ mcusys_on_off_latency
| u32 mt8186_mcucfg_regs::mcusys_on_off_latency |
◆ mcusys_par_wrap_dbg_mon
| u32 mt8186_mcucfg_regs::mcusys_par_wrap_dbg_mon |
◆ mcusys_par_wrap_dbg_mon_sel
| u32 mt8186_mcucfg_regs::mcusys_par_wrap_dbg_mon_sel |
◆ mcusys_pinmux
| u32 mt8186_mcucfg_regs::mcusys_pinmux |
◆ mcusys_pwr_ctrl
| u32 mt8186_mcucfg_regs::mcusys_pwr_ctrl |
◆ mcusys_reserved_reg0
| u32 mt8186_mcucfg_regs::mcusys_reserved_reg0 |
◆ mcusys_reserved_reg0_rd
| u32 mt8186_mcucfg_regs::mcusys_reserved_reg0_rd |
◆ mcusys_reserved_reg1
| u32 mt8186_mcucfg_regs::mcusys_reserved_reg1 |
◆ mcusys_reserved_reg1_rd
| u32 mt8186_mcucfg_regs::mcusys_reserved_reg1_rd |
◆ mcusys_reserved_reg2
| u32 mt8186_mcucfg_regs::mcusys_reserved_reg2 |
◆ mcusys_reserved_reg2_rd
| u32 mt8186_mcucfg_regs::mcusys_reserved_reg2_rd |
◆ mcusys_reserved_reg3
| u32 mt8186_mcucfg_regs::mcusys_reserved_reg3 |
◆ mcusys_reserved_reg3_rd
| u32 mt8186_mcucfg_regs::mcusys_reserved_reg3_rd |
◆ mcusys_spmc_pwr_status
| u32 mt8186_mcucfg_regs::mcusys_spmc_pwr_status |
◆ mcusys_spmc_sw_cfg
| u32 mt8186_mcucfg_regs::mcusys_spmc_sw_cfg |
◆ mcusys_spmc_wait_cfg
| u32 mt8186_mcucfg_regs::mcusys_spmc_wait_cfg |
◆ mp0_cluster_cfg0
| u32 mt8186_mcucfg_regs::mp0_cluster_cfg0 |
◆ mp0_cluster_cfg10
| u32 mt8186_mcucfg_regs::mp0_cluster_cfg10 |
◆ mp0_cluster_cfg11
| u32 mt8186_mcucfg_regs::mp0_cluster_cfg11 |
◆ mp0_cluster_cfg12
| u32 mt8186_mcucfg_regs::mp0_cluster_cfg12 |
◆ mp0_cluster_cfg13
| u32 mt8186_mcucfg_regs::mp0_cluster_cfg13 |
◆ mp0_cluster_cfg14
| u32 mt8186_mcucfg_regs::mp0_cluster_cfg14 |
◆ mp0_cluster_cfg15
| u32 mt8186_mcucfg_regs::mp0_cluster_cfg15 |
◆ mp0_cluster_cfg16
| u32 mt8186_mcucfg_regs::mp0_cluster_cfg16 |
◆ mp0_cluster_cfg17
| u32 mt8186_mcucfg_regs::mp0_cluster_cfg17 |
◆ mp0_cluster_cfg18
| u32 mt8186_mcucfg_regs::mp0_cluster_cfg18 |
◆ mp0_cluster_cfg19
| u32 mt8186_mcucfg_regs::mp0_cluster_cfg19 |
◆ mp0_cluster_cfg20
| u32 mt8186_mcucfg_regs::mp0_cluster_cfg20 |
◆ mp0_cluster_cfg21
| u32 mt8186_mcucfg_regs::mp0_cluster_cfg21 |
◆ mp0_cluster_cfg22
| u32 mt8186_mcucfg_regs::mp0_cluster_cfg22 |
◆ mp0_cluster_cfg23
| u32 mt8186_mcucfg_regs::mp0_cluster_cfg23 |
◆ mp0_cluster_cfg4
| u32 mt8186_mcucfg_regs::mp0_cluster_cfg4 |
◆ mp0_cluster_cfg5
| u32 mt8186_mcucfg_regs::mp0_cluster_cfg5 |
◆ mp0_cluster_cfg6
| u32 mt8186_mcucfg_regs::mp0_cluster_cfg6 |
◆ mp0_cluster_cfg7
| u32 mt8186_mcucfg_regs::mp0_cluster_cfg7 |
◆ mp0_cluster_cfg8
| u32 mt8186_mcucfg_regs::mp0_cluster_cfg8 |
◆ mp0_cluster_cfg9
| u32 mt8186_mcucfg_regs::mp0_cluster_cfg9 |
◆ mp0_cpu0_dc_age
| u32 mt8186_mcucfg_regs::mp0_cpu0_dc_age |
◆ mp0_cpu0_nonwfx_cnt
| u32 mt8186_mcucfg_regs::mp0_cpu0_nonwfx_cnt |
◆ mp0_cpu0_nonwfx_ctrl
| u32 mt8186_mcucfg_regs::mp0_cpu0_nonwfx_ctrl |
◆ mp0_cpu1_dc_age
| u32 mt8186_mcucfg_regs::mp0_cpu1_dc_age |
◆ mp0_cpu1_nonwfx_cnt
| u32 mt8186_mcucfg_regs::mp0_cpu1_nonwfx_cnt |
◆ mp0_cpu1_nonwfx_ctrl
| u32 mt8186_mcucfg_regs::mp0_cpu1_nonwfx_ctrl |
◆ mp0_cpu2_dc_age
| u32 mt8186_mcucfg_regs::mp0_cpu2_dc_age |
◆ mp0_cpu2_nonwfx_cnt
| u32 mt8186_mcucfg_regs::mp0_cpu2_nonwfx_cnt |
◆ mp0_cpu2_nonwfx_ctrl
| u32 mt8186_mcucfg_regs::mp0_cpu2_nonwfx_ctrl |
◆ mp0_cpu3_dc_age
| u32 mt8186_mcucfg_regs::mp0_cpu3_dc_age |
◆ mp0_cpu3_nonwfx_cnt
| u32 mt8186_mcucfg_regs::mp0_cpu3_nonwfx_cnt |
◆ mp0_cpu3_nonwfx_ctrl
| u32 mt8186_mcucfg_regs::mp0_cpu3_nonwfx_ctrl |
◆ mp0_cpu4_dc_age
| u32 mt8186_mcucfg_regs::mp0_cpu4_dc_age |
◆ mp0_cpu4_nonwfx_cnt
| u32 mt8186_mcucfg_regs::mp0_cpu4_nonwfx_cnt |
◆ mp0_cpu4_nonwfx_ctrl
| u32 mt8186_mcucfg_regs::mp0_cpu4_nonwfx_ctrl |
◆ mp0_cpu5_dc_age
| u32 mt8186_mcucfg_regs::mp0_cpu5_dc_age |
◆ mp0_cpu5_nonwfx_cnt
| u32 mt8186_mcucfg_regs::mp0_cpu5_nonwfx_cnt |
◆ mp0_cpu5_nonwfx_ctrl
| u32 mt8186_mcucfg_regs::mp0_cpu5_nonwfx_ctrl |
◆ mp0_cpu6_dc_age
| u32 mt8186_mcucfg_regs::mp0_cpu6_dc_age |
◆ mp0_cpu6_nonwfx_cnt
| u32 mt8186_mcucfg_regs::mp0_cpu6_nonwfx_cnt |
◆ mp0_cpu6_nonwfx_ctrl
| u32 mt8186_mcucfg_regs::mp0_cpu6_nonwfx_ctrl |
◆ mp0_cpu7_dc_age
| u32 mt8186_mcucfg_regs::mp0_cpu7_dc_age |
◆ mp0_cpu7_nonwfx_cnt
| u32 mt8186_mcucfg_regs::mp0_cpu7_nonwfx_cnt |
◆ mp0_cpu7_nonwfx_ctrl
| u32 mt8186_mcucfg_regs::mp0_cpu7_nonwfx_ctrl |
◆ mp0_dbg_mon
| u32 mt8186_mcucfg_regs::mp0_dbg_mon |
◆ mp0_dbg_mon_sel
| u32 mt8186_mcucfg_regs::mp0_dbg_mon_sel |
◆ mp0_dcm_cfg0
| u32 mt8186_mcucfg_regs::mp0_dcm_cfg0 |
◆ mp0_dcm_cfg1
| u32 mt8186_mcucfg_regs::mp0_dcm_cfg1 |
◆ mp0_dcm_cfg2
| u32 mt8186_mcucfg_regs::mp0_dcm_cfg2 |
◆ mp0_dcm_cfg3
| u32 mt8186_mcucfg_regs::mp0_dcm_cfg3 |
◆ mp0_dcm_cfg4
| u32 mt8186_mcucfg_regs::mp0_dcm_cfg4 |
◆ mp0_dcm_cfg5
| u32 mt8186_mcucfg_regs::mp0_dcm_cfg5 |
◆ mp0_dcm_cfg6
| u32 mt8186_mcucfg_regs::mp0_dcm_cfg6 |
◆ mp0_dcm_cfg7
| u32 mt8186_mcucfg_regs::mp0_dcm_cfg7 |
◆ mp0_dcm_cfg8
| u32 mt8186_mcucfg_regs::mp0_dcm_cfg8 |
◆ mp0_l3_cache_parity1
| u32 mt8186_mcucfg_regs::mp0_l3_cache_parity1 |
◆ mp0_l3_cache_parity2
| u32 mt8186_mcucfg_regs::mp0_l3_cache_parity2 |
◆ mp0_l3_cache_parity3
| u32 mt8186_mcucfg_regs::mp0_l3_cache_parity3 |
◆ mp0_l3_data_ram_delsel
| u32 mt8186_mcucfg_regs::mp0_l3_data_ram_delsel |
◆ mp0_l3_scu_sf_ram_delsel
| u32 mt8186_mcucfg_regs::mp0_l3_scu_sf_ram_delsel |
◆ mp0_l3_tag_ram_delsel
| u32 mt8186_mcucfg_regs::mp0_l3_tag_ram_delsel |
◆ mp0_l3_victim_ram_delsel
| u32 mt8186_mcucfg_regs::mp0_l3_victim_ram_delsel |
◆ mp0_ses_apb_trig
| u32 mt8186_mcucfg_regs::mp0_ses_apb_trig |
◆ mp0_victim_rd_mask
| u32 mt8186_mcucfg_regs::mp0_victim_rd_mask |
◆ mp_adb_dcm_cfg0
| u32 mt8186_mcucfg_regs::mp_adb_dcm_cfg0 |
◆ mp_adb_dcm_cfg2
| u32 mt8186_mcucfg_regs::mp_adb_dcm_cfg2 |
◆ mp_adb_dcm_cfg4
| u32 mt8186_mcucfg_regs::mp_adb_dcm_cfg4 |
◆ mp_misc_dcm_cfg0
| u32 mt8186_mcucfg_regs::mp_misc_dcm_cfg0 |
◆ mp_top_dbg_mon
| u32 mt8186_mcucfg_regs::mp_top_dbg_mon |
◆ mp_top_dbg_mon_sel
| u32 mt8186_mcucfg_regs::mp_top_dbg_mon_sel |
◆ pikachu_event
| u32 mt8186_mcucfg_regs::pikachu_event |
◆ pikachu_status
| u32 mt8186_mcucfg_regs::pikachu_status |
◆ pllbuck_group_func
| u32 mt8186_mcucfg_regs::pllbuck_group_func |
◆ plldiv_big_reserved
| u32 mt8186_mcucfg_regs::plldiv_big_reserved |
◆ plldiv_bus_reserved
| u32 mt8186_mcucfg_regs::plldiv_bus_reserved |
◆ plldiv_ctl0
| u32 mt8186_mcucfg_regs::plldiv_ctl0 |
◆ plldiv_imax_cg
| u32 mt8186_mcucfg_regs::plldiv_imax_cg |
◆ plldiv_imax_detector
| u32 mt8186_mcucfg_regs::plldiv_imax_detector |
◆ plldiv_imax_int
| u32 mt8186_mcucfg_regs::plldiv_imax_int |
◆ plldiv_little_reserved
| u32 mt8186_mcucfg_regs::plldiv_little_reserved |
◆ plldiv_percore_dfs_1
| u32 mt8186_mcucfg_regs::plldiv_percore_dfs_1 |
◆ plldiv_percore_dfs_2
| u32 mt8186_mcucfg_regs::plldiv_percore_dfs_2 |
◆ plldiv_turbo
| u32 mt8186_mcucfg_regs::plldiv_turbo |
◆ reserved1
| u32 mt8186_mcucfg_regs::reserved1[2] |
◆ reserved10
| u32 mt8186_mcucfg_regs::reserved10[4] |
◆ reserved11
| u32 mt8186_mcucfg_regs::reserved11[5] |
◆ reserved12
| u32 mt8186_mcucfg_regs::reserved12[20] |
◆ reserved13
| u32 mt8186_mcucfg_regs::reserved13[5] |
◆ reserved14
| u32 mt8186_mcucfg_regs::reserved14[4] |
◆ reserved15
| u32 mt8186_mcucfg_regs::reserved15[7] |
◆ reserved16
| u32 mt8186_mcucfg_regs::reserved16[5] |
◆ reserved17
| u32 mt8186_mcucfg_regs::reserved17[4] |
◆ reserved18
| u32 mt8186_mcucfg_regs::reserved18[39] |
◆ reserved19
| u32 mt8186_mcucfg_regs::reserved19[1] |
◆ reserved2
| u32 mt8186_mcucfg_regs::reserved2[2] |
◆ reserved20
| u32 mt8186_mcucfg_regs::reserved20[52] |
◆ reserved21
| u32 mt8186_mcucfg_regs::reserved21[48] |
◆ reserved22
| u32 mt8186_mcucfg_regs::reserved22[3] |
◆ reserved23
| u32 mt8186_mcucfg_regs::reserved23[3] |
◆ reserved24
| u32 mt8186_mcucfg_regs::reserved24[1667] |
◆ reserved25
| u32 mt8186_mcucfg_regs::reserved25[21] |
◆ reserved26
| u32 mt8186_mcucfg_regs::reserved26[64] |
◆ reserved27
| u32 mt8186_mcucfg_regs::reserved27[1] |
◆ reserved28
| u32 mt8186_mcucfg_regs::reserved28[1] |
◆ reserved29
| u32 mt8186_mcucfg_regs::reserved29[2] |
◆ reserved3
| u32 mt8186_mcucfg_regs::reserved3[3] |
◆ reserved30
| u32 mt8186_mcucfg_regs::reserved30[11] |
◆ reserved31
| u32 mt8186_mcucfg_regs::reserved31[9] |
◆ reserved32
| u32 mt8186_mcucfg_regs::reserved32[13] |
◆ reserved33
| u32 mt8186_mcucfg_regs::reserved33[3] |
◆ reserved34
| u32 mt8186_mcucfg_regs::reserved34[3] |
◆ reserved35
| u32 mt8186_mcucfg_regs::reserved35[6] |
◆ reserved36
| u32 mt8186_mcucfg_regs::reserved36[23] |
◆ reserved37
| u32 mt8186_mcucfg_regs::reserved37[31] |
◆ reserved38
| u32 mt8186_mcucfg_regs::reserved38[3] |
◆ reserved39
| u32 mt8186_mcucfg_regs::reserved39[7] |
◆ reserved4
| u32 mt8186_mcucfg_regs::reserved4[5] |
◆ reserved40
| u32 mt8186_mcucfg_regs::reserved40[46] |
◆ reserved41
| u32 mt8186_mcucfg_regs::reserved41[1] |
◆ reserved42
| u32 mt8186_mcucfg_regs::reserved42[1] |
◆ reserved43
| u32 mt8186_mcucfg_regs::reserved43[1] |
◆ reserved44
| u32 mt8186_mcucfg_regs::reserved44[9] |
◆ reserved45
| u32 mt8186_mcucfg_regs::reserved45[15] |
◆ reserved46
| u32 mt8186_mcucfg_regs::reserved46[5] |
◆ reserved47
| u32 mt8186_mcucfg_regs::reserved47[7] |
◆ reserved48
| u32 mt8186_mcucfg_regs::reserved48[15] |
◆ reserved49
| u32 mt8186_mcucfg_regs::reserved49[1] |
◆ reserved5
| u32 mt8186_mcucfg_regs::reserved5[8] |
◆ reserved50
| u32 mt8186_mcucfg_regs::reserved50[9] |
◆ reserved51
| u32 mt8186_mcucfg_regs::reserved51[45] |
◆ reserved52
| u32 mt8186_mcucfg_regs::reserved52[1] |
◆ reserved53
| u32 mt8186_mcucfg_regs::reserved53[5] |
◆ reserved54
| u32 mt8186_mcucfg_regs::reserved54[3] |
◆ reserved55
| u32 mt8186_mcucfg_regs::reserved55[1] |
◆ reserved56
| u32 mt8186_mcucfg_regs::reserved56[20] |
◆ reserved57
| u32 mt8186_mcucfg_regs::reserved57[1] |
◆ reserved58
| u32 mt8186_mcucfg_regs::reserved58[4] |
◆ reserved59
| u32 mt8186_mcucfg_regs::reserved59[27] |
◆ reserved6
| u32 mt8186_mcucfg_regs::reserved6[10] |
◆ reserved60
| u32 mt8186_mcucfg_regs::reserved60[58] |
◆ reserved61
| u32 mt8186_mcucfg_regs::reserved61[29] |
◆ reserved62
| u32 mt8186_mcucfg_regs::reserved62[2] |
◆ reserved63
| u32 mt8186_mcucfg_regs::reserved63[1] |
◆ reserved64
| u32 mt8186_mcucfg_regs::reserved64[2] |
◆ reserved65
| u32 mt8186_mcucfg_regs::reserved65[88] |
◆ reserved66
| u32 mt8186_mcucfg_regs::reserved66[63] |
◆ reserved67
| u32 mt8186_mcucfg_regs::reserved67[126] |
◆ reserved68
| u32 mt8186_mcucfg_regs::reserved68[125] |
◆ reserved69
| u32 mt8186_mcucfg_regs::reserved69[125] |
◆ reserved7
| u32 mt8186_mcucfg_regs::reserved7[4] |
◆ reserved70
| u32 mt8186_mcucfg_regs::reserved70[125] |
◆ reserved71
| u32 mt8186_mcucfg_regs::reserved71[125] |
◆ reserved72
| u32 mt8186_mcucfg_regs::reserved72[125] |
◆ reserved73
| u32 mt8186_mcucfg_regs::reserved73[125] |
◆ reserved74
| u32 mt8186_mcucfg_regs::reserved74[125] |
◆ reserved75
| u32 mt8186_mcucfg_regs::reserved75[125] |
◆ reserved76
| u32 mt8186_mcucfg_regs::reserved76[528] |
◆ reserved77
| u32 mt8186_mcucfg_regs::reserved77[12] |
◆ reserved78
| u32 mt8186_mcucfg_regs::reserved78[7] |
◆ reserved79
| u32 mt8186_mcucfg_regs::reserved79[1] |
◆ reserved8
| u32 mt8186_mcucfg_regs::reserved8[51] |
◆ reserved80
| u32 mt8186_mcucfg_regs::reserved80[3] |
◆ reserved81
| u32 mt8186_mcucfg_regs::reserved81[4] |
◆ reserved82
| u32 mt8186_mcucfg_regs::reserved82[1] |
◆ reserved83
| u32 mt8186_mcucfg_regs::reserved83[174] |
◆ reserved84
| u32 mt8186_mcucfg_regs::reserved84[7] |
◆ reserved85
| u32 mt8186_mcucfg_regs::reserved85[53] |
◆ reserved86
| u32 mt8186_mcucfg_regs::reserved86[3] |
◆ reserved87
| u32 mt8186_mcucfg_regs::reserved87[3] |
◆ reserved88
| u32 mt8186_mcucfg_regs::reserved88[53] |
◆ reserved89
| u32 mt8186_mcucfg_regs::reserved89[3183] |
◆ reserved9
| u32 mt8186_mcucfg_regs::reserved9[5] |
◆ sclk_cfg_slow_down_ck
| u32 mt8186_mcucfg_regs::sclk_cfg_slow_down_ck |
◆ sec_pol_ctl_en0
| u32 mt8186_mcucfg_regs::sec_pol_ctl_en0 |
◆ sec_pol_ctl_en1
| u32 mt8186_mcucfg_regs::sec_pol_ctl_en1 |
◆ sec_pol_ctl_en10
| u32 mt8186_mcucfg_regs::sec_pol_ctl_en10 |
◆ sec_pol_ctl_en11
| u32 mt8186_mcucfg_regs::sec_pol_ctl_en11 |
◆ sec_pol_ctl_en12
| u32 mt8186_mcucfg_regs::sec_pol_ctl_en12 |
◆ sec_pol_ctl_en13
| u32 mt8186_mcucfg_regs::sec_pol_ctl_en13 |
◆ sec_pol_ctl_en14
| u32 mt8186_mcucfg_regs::sec_pol_ctl_en14 |
◆ sec_pol_ctl_en15
| u32 mt8186_mcucfg_regs::sec_pol_ctl_en15 |
◆ sec_pol_ctl_en16
| u32 mt8186_mcucfg_regs::sec_pol_ctl_en16 |
◆ sec_pol_ctl_en17
| u32 mt8186_mcucfg_regs::sec_pol_ctl_en17 |
◆ sec_pol_ctl_en18
| u32 mt8186_mcucfg_regs::sec_pol_ctl_en18 |
◆ sec_pol_ctl_en19
| u32 mt8186_mcucfg_regs::sec_pol_ctl_en19 |
◆ sec_pol_ctl_en2
| u32 mt8186_mcucfg_regs::sec_pol_ctl_en2 |
◆ sec_pol_ctl_en3
| u32 mt8186_mcucfg_regs::sec_pol_ctl_en3 |
◆ sec_pol_ctl_en4
| u32 mt8186_mcucfg_regs::sec_pol_ctl_en4 |
◆ sec_pol_ctl_en5
| u32 mt8186_mcucfg_regs::sec_pol_ctl_en5 |
◆ sec_pol_ctl_en6
| u32 mt8186_mcucfg_regs::sec_pol_ctl_en6 |
◆ sec_pol_ctl_en7
| u32 mt8186_mcucfg_regs::sec_pol_ctl_en7 |
◆ sec_pol_ctl_en8
| u32 mt8186_mcucfg_regs::sec_pol_ctl_en8 |
◆ sec_pol_ctl_en9
| u32 mt8186_mcucfg_regs::sec_pol_ctl_en9 |
◆ spmc_dbg_setting
| u32 mt8186_mcucfg_regs::spmc_dbg_setting |
◆ sw_gic_wakeup_req
| u32 mt8186_mcucfg_regs::sw_gic_wakeup_req |
◆ systime_base_h
| u32 mt8186_mcucfg_regs::systime_base_h |
◆ systime_base_l
| u32 mt8186_mcucfg_regs::systime_base_l |
◆ trace_data_entry0_h
| u32 mt8186_mcucfg_regs::trace_data_entry0_h |
◆ trace_data_entry0_l
| u32 mt8186_mcucfg_regs::trace_data_entry0_l |
◆ trace_data_entry1_h
| u32 mt8186_mcucfg_regs::trace_data_entry1_h |
◆ trace_data_entry1_l
| u32 mt8186_mcucfg_regs::trace_data_entry1_l |
◆ trace_data_entry2_h
| u32 mt8186_mcucfg_regs::trace_data_entry2_h |
◆ trace_data_entry2_l
| u32 mt8186_mcucfg_regs::trace_data_entry2_l |
◆ trace_data_entry3_h
| u32 mt8186_mcucfg_regs::trace_data_entry3_h |
◆ trace_data_entry3_l
| u32 mt8186_mcucfg_regs::trace_data_entry3_l |
◆ trace_data_selection
| u32 mt8186_mcucfg_regs::trace_data_selection |
◆ udi_cfg0
| u32 mt8186_mcucfg_regs::udi_cfg0 |
◆ udi_cfg1
| u32 mt8186_mcucfg_regs::udi_cfg1 |
◆ wfx_ret_met_dbc_sel
| u32 mt8186_mcucfg_regs::wfx_ret_met_dbc_sel |
The documentation for this struct was generated from the following file:
- src/soc/mediatek/mt8186/include/soc/mcucfg.h
1.9.1