coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
romstage.c
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #include <fsp/api.h>
4 #include <FspmUpd.h>
7 #include <soc/romstage.h>
8 #include <string.h>
9 #include <gpio.h>
11 #include <skxsp_tp_iio.h>
12 
13 #include "ipmi.h"
14 
16 
17 static void oem_update_iio(FSPM_UPD *mupd)
18 {
19  /* Read GPIO to decide IIO bifurcation at run-time. */
20  int slot_config0 = gpio_get(GPP_C15);
21  int slot_config1 = gpio_get(GPP_C16);
22 
23  /* It's a single side 3 slots riser card, to tell which AICs are on each slot requires
24  reading the GPIO expander PCA9555 via SMBUS, and then configure the bifurcation
25  accordingly is left for future work. */
26  if (!slot_config0 && slot_config1)
27  mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable[Skt0_Iou0].Bifurcation
28  = IIO_BIFURCATE_xxx8xxx8;
29 }
30 
31 static void mainboard_config_iio(FSPM_UPD *mupd)
32 {
34  mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable =
35  (UPD_IIO_BIFURCATION_DATA_ENTRY *) iio_table_buf;
36  mupd->FspmConfig.IioBifurcationConfig.NumberOfEntries =
38 
39  mupd->FspmConfig.IioPciConfig.ConfigurationTable =
40  (UPD_PCI_PORT_CONFIG *) tp_iio_pci_port_skt0;
41  mupd->FspmConfig.IioPciConfig.NumberOfEntries =
43 
44  mupd->FspmConfig.PchPciConfig.PciPortConfig =
45  (UPD_PCH_PCIE_PORT *) tp_pch_pci_port_skt0;
46  mupd->FspmConfig.PchPciConfig.NumberOfEntries =
48 
49  mupd->FspmConfig.PchPciConfig.RootPortFunctionSwapping = 0x00;
50  mupd->FspmConfig.PchPciConfig.PciePllSsc = 0x00;
51  oem_update_iio(mupd);
52 }
53 
54 void mainboard_memory_init_params(FSPM_UPD *mupd)
55 {
56  /* It's better to run get BMC selftest result first */
57  if (ipmi_kcs_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) {
58  ipmi_set_post_start(CONFIG_BMC_KCS_BASE);
59  init_frb2_wdt();
60  }
62 
63  /* do not configure GPIO controller inside FSP-M */
64  mupd->FspmConfig.GpioConfig.GpioTable = NULL;
65  mupd->FspmConfig.GpioConfig.NumberOfEntries = 0;
66 }
#define GPP_C15
#define GPP_C16
void * memcpy(void *dest, const void *src, size_t n)
Definition: memcpy.c:7
#define ARRAY_SIZE(a)
Definition: helpers.h:12
@ CB_SUCCESS
Call completed successfully.
Definition: cb_err.h:16
void init_frb2_wdt(void)
Definition: ipmi.c:60
int gpio_get(gpio_t gpio)
Definition: gpio.c:166
enum cb_err ipmi_kcs_premem_init(const u16 port, const u16 device)
enum cb_err ipmi_set_post_start(const int port)
void mainboard_memory_init_params(FSPM_UPD *mupd)
Definition: romstage.c:22
static uint8_t iio_table_buf[sizeof(tp_iio_bifur_table)]
Definition: romstage.c:15
static void mainboard_config_iio(FSPM_UPD *mupd)
Definition: romstage.c:31
static void oem_update_iio(FSPM_UPD *mupd)
Definition: romstage.c:17
@ Skt0_Iou0
Definition: skxsp_tp_iio.h:10
static const UPD_PCI_PORT_CONFIG tp_iio_pci_port_skt0[]
Definition: skxsp_tp_iio.h:71
static const UPD_PCH_PCIE_PORT tp_pch_pci_port_skt0[]
Definition: skxsp_tp_iio.h:89
static const UPD_IIO_BIFURCATION_DATA_ENTRY tp_iio_bifur_table[]
Definition: skxsp_tp_iio.h:29
#define NULL
Definition: stddef.h:19
unsigned char uint8_t
Definition: stdint.h:8