coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
skxsp_tp_iio.h File Reference
#include <FspmUpd.h>
#include <soc/pci_devs.h>
Include dependency graph for skxsp_tp_iio.h:
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Go to the source code of this file.

Macros

#define CFG_UPD_PORT(port, hide)
 

Enumerations

enum  tp_iio_bifur_table_index {
  Skt0_Iou0 = 0 , Skt0_Iou1 , Skt0_Iou2 , Skt0_Mcp0 ,
  Skt0_Mcp1 , Skt1_Iou0 , Skt1_Iou1 , Skt1_Iou2 ,
  Skt1_Mcp0 , Skt1_Mcp1
}
 

Variables

static const UPD_IIO_BIFURCATION_DATA_ENTRY tp_iio_bifur_table []
 
static const UPD_PCI_PORT_CONFIG tp_iio_pci_port_skt0 []
 
static const UPD_PCH_PCIE_PORT tp_pch_pci_port_skt0 []
 

Macro Definition Documentation

◆ CFG_UPD_PORT

#define CFG_UPD_PORT (   port,
  hide 
)
Value:
{ \
.PortIndex = port, \
.HidePort = hide, \
.DeEmphasis = 0x00, \
.PortLinkSpeed = PcieAuto, \
.MaxPayload = 0x00, \
.DfxDnTxPreset = 0xFF, \
.DfxRxPreset = 0xFF, \
.DfxUpTxPreset = 0xFF, \
.Sris = 0x00, \
.PcieCommonClock = 0x00, \
.NtbPpd = NTB_PORT_TRANSPARENT, \
.NtbSplitBar = 0x00, \
.NtbBarSizePBar23 = 0x16, \
.NtbBarSizePBar4 = 0x16, \
.NtbBarSizePBar5 = 0x16, \
.NtbBarSizePBar45 = 0x16, \
.NtbBarSizeSBar23 = 0x16, \
.NtbBarSizeSBar4 = 0x16, \
.NtbBarSizeSBar5 = 0x16, \
.NtbBarSizeSBar45 = 0x16, \
.NtbSBar01Prefetch = 0x00, \
.NtbXlinkCtlOverride = 0x03, \
}
port
Definition: i915.h:29
@ PcieAuto
Definition: chip.h:28

Definition at line 42 of file skxsp_tp_iio.h.

Enumeration Type Documentation

◆ tp_iio_bifur_table_index

Enumerator
Skt0_Iou0 
Skt0_Iou1 
Skt0_Iou2 
Skt0_Mcp0 
Skt0_Mcp1 
Skt1_Iou0 
Skt1_Iou1 
Skt1_Iou2 
Skt1_Mcp0 
Skt1_Mcp1 

Definition at line 9 of file skxsp_tp_iio.h.

Variable Documentation

◆ tp_iio_bifur_table

const UPD_IIO_BIFURCATION_DATA_ENTRY tp_iio_bifur_table[]
static
Initial value:
= {
{ Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 },
{ Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 },
{ Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 },
{ Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxxxx },
{ Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx },
{ Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxxxx },
{ Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxxxx },
{ Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxx8xxx8 },
{ Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxxxx },
{ Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx },
}

Definition at line 29 of file skxsp_tp_iio.h.

Referenced by mainboard_config_iio().

◆ tp_iio_pci_port_skt0

const UPD_PCI_PORT_CONFIG tp_iio_pci_port_skt0[]
static
Initial value:
= {
CFG_UPD_PORT(PORT_1A, NOT_HIDE),
CFG_UPD_PORT(PORT_1B, HIDE),
CFG_UPD_PORT(PORT_1C, HIDE),
CFG_UPD_PORT(PORT_1D, HIDE),
CFG_UPD_PORT(PORT_2A, NOT_HIDE),
CFG_UPD_PORT(PORT_2B, HIDE),
CFG_UPD_PORT(PORT_2C, HIDE),
CFG_UPD_PORT(PORT_2D, HIDE),
CFG_UPD_PORT(PORT_3A, NOT_HIDE),
CFG_UPD_PORT(PORT_3B, HIDE),
CFG_UPD_PORT(PORT_3C, NOT_HIDE),
CFG_UPD_PORT(PORT_3D, HIDE),
}
#define CFG_UPD_PORT(port, hide)
Definition: skxsp_tp_iio.h:42

Definition at line 71 of file skxsp_tp_iio.h.

Referenced by mainboard_config_iio().

◆ tp_pch_pci_port_skt0

const UPD_PCH_PCIE_PORT tp_pch_pci_port_skt0[]
static
Initial value:
= {
{ 0x00, 0x00, PcieAuto },
{ 0x04, 0x00, PcieAuto },
{ 0x05, 0x00, PcieAuto },
}

Definition at line 89 of file skxsp_tp_iio.h.

Referenced by mainboard_config_iio().