3 #include <soc/romstage.h>
6 #include <fsp/soc_binding.h>
9 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
10 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
14 23, 21, 16, 17, 18, 19, 22, 20, 3, 5, 2, 4, 7, 0, 6, 1,
15 24, 27, 26, 30, 28, 25, 29, 31, 13, 8, 12, 15, 10, 14, 11, 9,
19 10, 14, 12, 13, 9, 11, 15, 8, 1, 6, 2, 5, 0, 7, 3, 4,
20 21, 18, 19, 22, 20, 17, 16, 23, 29, 28, 24, 27, 31, 30, 26, 25,
24 13, 15, 10, 14, 9, 12, 8, 11, 22, 19, 16, 23, 21, 17, 20, 18,
25 26, 24, 28, 29, 31, 30, 27, 25, 4, 5, 1, 0, 3, 6, 7, 2,
29 0, 3, 6, 7, 4, 5, 1, 2, 20, 17, 21, 16, 23, 18, 22, 19,
30 15, 9, 11, 14, 12, 8, 13, 10, 26, 29, 24, 31, 25, 30, 27, 28,
35 mupd->FspmConfig.Profile = 33;
36 mupd->FspmConfig.DIMM0SPDAddress = 0xa0;
37 mupd->FspmConfig.DIMM1SPDAddress = 0xa4;
38 mupd->FspmConfig.Ch0_RankEnable = 0;
39 mupd->FspmConfig.Ch0_DeviceWidth = 0;
40 mupd->FspmConfig.Ch0_DramDensity = 0;
41 mupd->FspmConfig.Ch0_Option = 3;
42 mupd->FspmConfig.Ch1_RankEnable = 0;
43 mupd->FspmConfig.Ch1_DeviceWidth = 0;
44 mupd->FspmConfig.Ch1_DramDensity = 0;
45 mupd->FspmConfig.Ch1_Option = 3;
46 mupd->FspmConfig.Ch2_RankEnable = 0;
47 mupd->FspmConfig.Ch2_DeviceWidth = 0;
48 mupd->FspmConfig.Ch2_DramDensity = 0;
49 mupd->FspmConfig.Ch2_Option = 3;
50 mupd->FspmConfig.Ch3_RankEnable = 0;
51 mupd->FspmConfig.Ch3_DeviceWidth = 0;
52 mupd->FspmConfig.Ch3_DramDensity = 0;
53 mupd->FspmConfig.Ch3_Option = 3;
62 mupd->FspmConfig.Profile = 5;
63 mupd->FspmConfig.DIMM0SPDAddress = 0;
64 mupd->FspmConfig.DIMM1SPDAddress = 0;
65 mupd->FspmConfig.Ch0_RankEnable = 3;
66 mupd->FspmConfig.Ch0_DeviceWidth = 2;
67 mupd->FspmConfig.Ch0_DramDensity = 0;
68 mupd->FspmConfig.Ch0_Option = 3;
69 mupd->FspmConfig.Ch1_RankEnable = 3;
70 mupd->FspmConfig.Ch1_DeviceWidth = 2;
71 mupd->FspmConfig.Ch1_DramDensity = 0;
72 mupd->FspmConfig.Ch1_Option = 3;
73 mupd->FspmConfig.Ch2_RankEnable = 3;
74 mupd->FspmConfig.Ch2_DeviceWidth = 2;
75 mupd->FspmConfig.Ch2_DramDensity = 0;
76 mupd->FspmConfig.Ch2_Option = 3;
77 mupd->FspmConfig.Ch3_RankEnable = 3;
78 mupd->FspmConfig.Ch3_DeviceWidth = 2;
79 mupd->FspmConfig.Ch3_DramDensity = 0;
80 mupd->FspmConfig.Ch3_Option = 3;
93 mupd->FspmConfig.Package = 0;
94 mupd->FspmConfig.MemoryDown = 1;
95 mupd->FspmConfig.DDR3LPageSize = 0;
96 mupd->FspmConfig.DDR3LASR = 0;
97 mupd->FspmConfig.ScramblerSupport = 1;
98 mupd->FspmConfig.ChannelHashMask = 0;
99 mupd->FspmConfig.SliceHashMask = 0;
100 mupd->FspmConfig.InterleavedMode = 0;
101 mupd->FspmConfig.ChannelsSlicesEnable = 0;
102 mupd->FspmConfig.MinRefRate2xEnable = 0;
103 mupd->FspmConfig.DualRankSupportEnable = 1;
104 mupd->FspmConfig.DisableFastBoot = 0;
105 mupd->FspmConfig.RmtMode = 0;
106 mupd->FspmConfig.MemorySizeLimit = 0;
107 mupd->FspmConfig.LowMemoryMaxValue = 0;
108 mupd->FspmConfig.HighMemoryMaxValue = 0;
110 if (
CONFIG(BOARD_INTEL_APOLLOLAKE_RVP1))
void * memcpy(void *dest, const void *src, size_t n)
void mainboard_memory_init_params(FSPM_UPD *mupd)
static const uint8_t swizzling1_rvp2[]
static const uint8_t swizzling_rvp1[]
static const uint8_t swizzling3_rvp2[]
static const uint8_t swizzling2_rvp2[]
static void rvp2_fill_memory_params(FSPM_UPD *mupd)
static const uint8_t swizzling0_rvp2[]
static void rvp1_fill_memory_params(FSPM_UPD *mupd)