coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
devtree.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <device/device.h>
4 #include <device/pci_def.h>
5 #include <option.h>
6 #include <types.h>
7 #include <variants.h>
8 
10 
12 {
13  const unsigned int power_profile = get_uint_option("power_profile", fallback);
14  return power_profile < NUM_POWER_PROFILES ? power_profile : fallback;
15 }
16 
17 void devtree_update(void)
18 {
19  config_t *cfg = config_of_soc();
20 
21  struct soc_power_limits_config *soc_conf =
22  &cfg->power_limits_config;
23 
24  struct device *nic_dev = pcidev_on_root(0x0c, 0);
25 
26  /* Update PL1 & PL2 based on CMOS settings */
28  case PP_POWER_SAVER:
29  soc_conf->tdp_pl1_override = 6;
30  soc_conf->tdp_pl2_override = 10;
31  break;
32  case PP_BALANCED:
33  soc_conf->tdp_pl1_override = 10;
34  soc_conf->tdp_pl2_override = 15;
35  break;
36  case PP_PERFORMANCE:
37  soc_conf->tdp_pl1_override = 10;
38  soc_conf->tdp_pl2_override = 20;
39  break;
40  }
41 
42  /* Enable/Disable Wireless based on CMOS settings */
43  if (get_uint_option("wireless", 1) == 0)
44  nic_dev->enabled = 0;
45 
46  /* Enable/Disable Webcam based on CMOS settings */
47  if (get_uint_option("webcam", 1) == 0)
48  cfg->usb2_port[4].enable = 0;
49 }
DEVTREE_CONST struct device * pcidev_on_root(uint8_t dev, uint8_t fn)
Definition: device_const.c:260
#define config_of_soc()
Definition: device.h:394
void devtree_update(void)
Definition: devtree.c:11
enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback)
Definition: devtree.c:11
unsigned int get_uint_option(const char *name, const unsigned int fallback)
Definition: option.c:116
#define NUM_POWER_PROFILES
Definition: variants.h:13
cmos_power_profile
Definition: variants.h:8
@ PP_PERFORMANCE
Definition: variants.h:11
@ PP_POWER_SAVER
Definition: variants.h:9
@ PP_BALANCED
Definition: variants.h:10
Definition: device.h:107
unsigned int enabled
Definition: device.h:122