coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
memory.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <baseboard/variants.h>
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#include <gpio.h>
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#include <soc/meminit.h>
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#include <variant/gpio.h>
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static
const
struct
lpddr4_sku
skus
[] = {
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/*
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* K4F6E304HB-MGCJ - both logical channels While the parts
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* are listed at 16Gb there are 2 ranks per channel so indicate
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* the deneisty as 8Gb per rank.
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*/
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[0] = {
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.
speed
=
LP4_SPEED_2400
,
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.ch0_rank_density =
LP4_8Gb_DENSITY
,
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.ch1_rank_density =
LP4_8Gb_DENSITY
,
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.ch0_dual_rank = 1,
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.ch1_dual_rank = 1,
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.part_num =
"K4F6E304HB-MGCJ"
,
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},
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/* K4F8E304HB-MGCJ - both logical channels */
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[1] = {
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.speed =
LP4_SPEED_2400
,
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.ch0_rank_density =
LP4_8Gb_DENSITY
,
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.ch1_rank_density =
LP4_8Gb_DENSITY
,
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.part_num =
"K4F8E304HB-MGCJ"
,
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},
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/*
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* MT53B512M32D2NP-062WT:C - both logical channels. While the parts
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* are listed at 16Gb there are 2 ranks per channel so indicate
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* the deneisty as 8Gb per rank.
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*/
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[2] = {
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.speed =
LP4_SPEED_2400
,
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.ch0_rank_density =
LP4_8Gb_DENSITY
,
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.ch1_rank_density =
LP4_8Gb_DENSITY
,
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.ch0_dual_rank = 1,
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.ch1_dual_rank = 1,
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.part_num =
"MT53B512M32D2NP"
,
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.disable_periodic_retraining = 1,
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},
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/* MT53B256M32D1NP-062 WT:C - both logical channels */
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[3] = {
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.speed =
LP4_SPEED_2400
,
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.ch0_rank_density =
LP4_8Gb_DENSITY
,
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.ch1_rank_density =
LP4_8Gb_DENSITY
,
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.part_num =
"MT53B256M32D1NP"
,
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.disable_periodic_retraining = 1,
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},
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/*
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* H9HCNNNBPUMLHR-NLE - both logical channels. While the parts
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* are listed at 16Gb there are 2 ranks per channel so indicate the
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* density as 8Gb per rank.
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*/
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[4] = {
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.speed =
LP4_SPEED_2400
,
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.ch0_rank_density =
LP4_8Gb_DENSITY
,
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.ch1_rank_density =
LP4_8Gb_DENSITY
,
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.ch0_dual_rank = 1,
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.ch1_dual_rank = 1,
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.part_num =
"H9HCNNNBPUMLHR"
,
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},
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/* H9HCNNN8KUMLHR-NLE - both logical channels */
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[5] = {
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.speed =
LP4_SPEED_2400
,
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.ch0_rank_density =
LP4_8Gb_DENSITY
,
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.ch1_rank_density =
LP4_8Gb_DENSITY
,
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.part_num =
"H9HCNNN8KUMLHR"
,
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},
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/* Samsung 290 K4F6E304HB-MGCH 16Gb dual-ch */
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[0xe] = {
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.speed =
LP4_SPEED_2400
,
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.ch0_rank_density =
LP4_8Gb_DENSITY
,
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.ch1_rank_density =
LP4_8Gb_DENSITY
,
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.ch0_dual_rank = 1,
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.ch1_dual_rank = 1,
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.part_num =
"K4F6E304HB-MGCH"
,
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},
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/* Samsung 280 K4F8E304HB-MGCH 8Gb dual-ch */
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[0xf] = {
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.speed =
LP4_SPEED_2400
,
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.ch0_rank_density =
LP4_8Gb_DENSITY
,
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.ch1_rank_density =
LP4_8Gb_DENSITY
,
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.ch0_dual_rank = 0,
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.ch1_dual_rank = 0,
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.part_num =
"K4F8E304HB-MGCH"
,
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},
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};
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static
const
struct
lpddr4_cfg
lp4cfg
= {
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.
skus
=
skus
,
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.num_skus =
ARRAY_SIZE
(
skus
),
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.swizzle_config = &
baseboard_lpddr4_swizzle
,
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};
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const
struct
lpddr4_cfg
*
variant_lpddr4_config
(
void
)
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{
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return
&
lp4cfg
;
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}
LP4_SPEED_2400
@ LP4_SPEED_2400
Definition:
meminit.h:49
LP4_8Gb_DENSITY
@ LP4_8Gb_DENSITY
Definition:
meminit.h:56
ARRAY_SIZE
#define ARRAY_SIZE(a)
Definition:
helpers.h:12
variant_lpddr4_config
const struct lpddr4_cfg *__weak variant_lpddr4_config(void)
Definition:
memory.c:190
baseboard_lpddr4_swizzle
const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle
Definition:
memory.c:9
lp4cfg
static const struct lpddr4_cfg lp4cfg
Definition:
memory.c:91
skus
static const struct lpddr4_sku skus[]
Definition:
memory.c:8
lpddr4_cfg
Definition:
meminit.h:111
lpddr4_cfg::skus
const struct lpddr4_sku * skus
Definition:
meminit.h:112
lpddr4_sku
Definition:
meminit.h:101
lpddr4_sku::speed
int speed
Definition:
meminit.h:102
src
mainboard
google
reef
variants
pyro
memory.c
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