coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
memory.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <baseboard/variants.h>
4 #include <gpio.h>
5 #include <soc/meminit.h>
6 #include <variant/gpio.h>
7 
8 static const struct lpddr4_sku skus[] = {
9  /*
10  * K4F6E304HB-MGCJ - both logical channels While the parts
11  * are listed at 16Gb there are 2 ranks per channel so indicate
12  * the deneisty as 8Gb per rank.
13  */
14  [0] = {
16  .ch0_rank_density = LP4_8Gb_DENSITY,
17  .ch1_rank_density = LP4_8Gb_DENSITY,
18  .ch0_dual_rank = 1,
19  .ch1_dual_rank = 1,
20  .part_num = "K4F6E304HB-MGCJ",
21  },
22  /* K4F8E304HB-MGCJ - both logical channels */
23  [1] = {
24  .speed = LP4_SPEED_2400,
25  .ch0_rank_density = LP4_8Gb_DENSITY,
26  .ch1_rank_density = LP4_8Gb_DENSITY,
27  .part_num = "K4F8E304HB-MGCJ",
28  },
29  /*
30  * MT53B512M32D2NP-062WT:C - both logical channels. While the parts
31  * are listed at 16Gb there are 2 ranks per channel so indicate
32  * the deneisty as 8Gb per rank.
33  */
34  [2] = {
35  .speed = LP4_SPEED_2400,
36  .ch0_rank_density = LP4_8Gb_DENSITY,
37  .ch1_rank_density = LP4_8Gb_DENSITY,
38  .ch0_dual_rank = 1,
39  .ch1_dual_rank = 1,
40  .part_num = "MT53B512M32D2NP",
41  .disable_periodic_retraining = 1,
42  },
43  /* MT53B256M32D1NP-062 WT:C - both logical channels */
44  [3] = {
45  .speed = LP4_SPEED_2400,
46  .ch0_rank_density = LP4_8Gb_DENSITY,
47  .ch1_rank_density = LP4_8Gb_DENSITY,
48  .part_num = "MT53B256M32D1NP",
49  .disable_periodic_retraining = 1,
50  },
51  /*
52  * H9HCNNNBPUMLHR-NLE - both logical channels. While the parts
53  * are listed at 16Gb there are 2 ranks per channel so indicate the
54  * density as 8Gb per rank.
55  */
56  [4] = {
57  .speed = LP4_SPEED_2400,
58  .ch0_rank_density = LP4_8Gb_DENSITY,
59  .ch1_rank_density = LP4_8Gb_DENSITY,
60  .ch0_dual_rank = 1,
61  .ch1_dual_rank = 1,
62  .part_num = "H9HCNNNBPUMLHR",
63  },
64  /* H9HCNNN8KUMLHR-NLE - both logical channels */
65  [5] = {
66  .speed = LP4_SPEED_2400,
67  .ch0_rank_density = LP4_8Gb_DENSITY,
68  .ch1_rank_density = LP4_8Gb_DENSITY,
69  .part_num = "H9HCNNN8KUMLHR",
70  },
71  /* Samsung 290 K4F6E304HB-MGCH 16Gb dual-ch */
72  [0xe] = {
73  .speed = LP4_SPEED_2400,
74  .ch0_rank_density = LP4_8Gb_DENSITY,
75  .ch1_rank_density = LP4_8Gb_DENSITY,
76  .ch0_dual_rank = 1,
77  .ch1_dual_rank = 1,
78  .part_num = "K4F6E304HB-MGCH",
79  },
80  /* Samsung 280 K4F8E304HB-MGCH 8Gb dual-ch */
81  [0xf] = {
82  .speed = LP4_SPEED_2400,
83  .ch0_rank_density = LP4_8Gb_DENSITY,
84  .ch1_rank_density = LP4_8Gb_DENSITY,
85  .ch0_dual_rank = 0,
86  .ch1_dual_rank = 0,
87  .part_num = "K4F8E304HB-MGCH",
88  },
89 };
90 
91 static const struct lpddr4_cfg lp4cfg = {
92  .skus = skus,
93  .num_skus = ARRAY_SIZE(skus),
94  .swizzle_config = &baseboard_lpddr4_swizzle,
95 };
96 
97 const struct lpddr4_cfg *variant_lpddr4_config(void)
98 {
99  return &lp4cfg;
100 }
@ LP4_SPEED_2400
Definition: meminit.h:49
@ LP4_8Gb_DENSITY
Definition: meminit.h:56
#define ARRAY_SIZE(a)
Definition: helpers.h:12
const struct lpddr4_cfg *__weak variant_lpddr4_config(void)
Definition: memory.c:190
const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle
Definition: memory.c:9
static const struct lpddr4_cfg lp4cfg
Definition: memory.c:91
static const struct lpddr4_sku skus[]
Definition: memory.c:8
const struct lpddr4_sku * skus
Definition: meminit.h:112
int speed
Definition: meminit.h:102