3 #ifndef _SOC_DISPLAY_DSI_PHY_H
4 #define _SOC_DISPLAY_DSI_PHY_H
9 #define MAX_REGULATOR_CONFIG 7
10 #define MAX_BIST_CONFIG 6
11 #define MAX_TIMING_CONFIG 40
12 #define MAX_LANE_CONFIG 45
13 #define MAX_STRENGTH_CONFIG 10
14 #define MAX_CTRL_CONFIG 4
15 #define DMA_TPG_FIFO_LEN 64
17 struct msm_panel_info;
cb_err
coreboot error codes
#define MAX_TIMING_CONFIG
enum cb_err mdss_dsi_phy_10nm_init(struct edid *edid, uint32_t num_of_lanes, uint32_t bpp)
#define MAX_STRENGTH_CONFIG
@ DSI_PHY_REGULATOR_DCDC_MODE
@ DSI_PHY_REGULATOR_LDO_MODE
#define MAX_REGULATOR_CONFIG
uint32_t timing[MAX_TIMING_CONFIG]
char laneCfg[MAX_LANE_CONFIG]
uint32_t strength[MAX_STRENGTH_CONFIG]
char bistCtrl[MAX_BIST_CONFIG]
uint32_t ctrl[MAX_CTRL_CONFIG]
enum dsi_reg_mode regulator_mode
uint32_t regulator[MAX_REGULATOR_CONFIG]
uint32_t half_byte_clk_en