coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Functions | |
void | uart_pll_vote_clk_enable (unsigned int clk_dummy) |
uart_pll_vote_clk_enable - enables PLL8 More... | |
static void | uart_set_rate_mnd (unsigned int gsbi_port, unsigned int m, unsigned int n) |
uart_set_rate_mnd - configures divider M and D values More... | |
static void | uart_branch_clk_enable_reg (unsigned int gsbi_port) |
uart_branch_clk_enable_reg - enables branch clock More... | |
static void | uart_local_clock_enable (unsigned int gsbi_port, unsigned int n, unsigned int m) |
uart_local_clock_enable - configures N value and enables root clocks More... | |
static void | uart_set_gsbi_clk (unsigned int gsbi_port) |
uart_set_gsbi_clk - enables HCLK for UART GSBI port More... | |
void | uart_clock_config (unsigned int gsbi_port, unsigned int m, unsigned int n, unsigned int d, unsigned int clk_dummy) |
uart_clock_config - configures UART clocks More... | |
void | nand_clock_config (void) |
nand_clock_config - configure NAND controller clocks More... | |
void | usb_clock_config (void) |
usb_clock_config - configure USB controller clocks and reset the controller More... | |
nand_clock_config - configure NAND controller clocks
Enable clocks to EBI2. Must be invoked before touching EBI2 registers.
Definition at line 113 of file clock.c.
References ALWAYS_ON_CLK_BRANCH_ENA, CLK_BRANCH_ENA, EBI2_CLK_CTL_REG, udelay(), and write32().
uart_branch_clk_enable_reg - enables branch clock
Enables branch clock for GSBI UART port.
Definition at line 41 of file clock.c.
References BIT, GSBIn_UART_APPS_NS_REG, and setbits32.
Referenced by uart_local_clock_enable().
void uart_clock_config | ( | unsigned int | gsbi_port, |
unsigned int | m, | ||
unsigned int | n, | ||
unsigned int | d, | ||
unsigned int | clk_dummy | ||
) |
uart_clock_config - configures UART clocks
Configures GSBI UART dividers, enable root and branch clocks.
Definition at line 98 of file clock.c.
References m, uart_local_clock_enable(), uart_pll_vote_clk_enable(), uart_set_gsbi_clk(), and uart_set_rate_mnd().
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uart_local_clock_enable - configures N value and enables root clocks
Sets the N parameter of the divider and enables root clock and branch clocks for GSBI UART port.
Definition at line 52 of file clock.c.
References BIT, BIT_POS_16, BIT_POS_31, GSBIn_UART_APPS_NS_REG, m, NS, read32(), uart_branch_clk_enable_reg(), Uart_clk_ns_mask, Uart_en_mask, and write32().
Referenced by uart_clock_config().
uart_pll_vote_clk_enable - enables PLL8
Definition at line 11 of file clock.c.
References BB_PLL_ENA_SC0_REG, BIT, PLL_LOCK_DET_STATUS_REG, read32(), and setbits32.
Referenced by uart_clock_config().
uart_set_gsbi_clk - enables HCLK for UART GSBI port
Definition at line 88 of file clock.c.
References BIT, GSBIn_HCLK_CTL_REG, and setbits32.
Referenced by uart_clock_config().
uart_set_rate_mnd - configures divider M and D values
Sets the M, D parameters of the divider to generate the GSBI UART apps clock.
Definition at line 25 of file clock.c.
References BIT, clrbits32, GSBIn_UART_APPS_MD_REG, GSBIn_UART_APPS_NS_REG, m, MD16, setbits32, and write32().
Referenced by uart_clock_config().
usb_clock_config - configure USB controller clocks and reset the controller
Definition at line 125 of file clock.c.
References udelay(), USB30_1_MASTER_CLK_CTL_REG, USB30_1_MOC_UTMI_CLK_CTL, USB30_MASTER_CLK_CTL_REG, USB30_MASTER_CLK_MD, USB30_MASTER_CLK_NS, USB30_MOC_UTMI_CLK_CTL, USB30_MOC_UTMI_CLK_MD, USB30_MOC_UTMI_CLK_NS, USB30_RESET, and write32().