coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
fixme.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <arch/hpet.h>
4 #include <cpu/x86/mtrr.h>
5 #include <cpu/amd/msr.h>
6 #include <cpu/amd/mtrr.h>
8 #include <Porting.h>
9 #include <AGESA.h>
10 #include <amdlib.h>
11 
12 void amd_initcpuio(void)
13 {
14  UINT64 MsrReg;
15  UINT32 PciData;
16  PCI_ADDR PciAddress;
17  AMD_CONFIG_PARAMS StdHeader;
18 
19  /* Enable legacy video routing: D18F1xF4 VGA Enable */
20  PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);
21  PciData = 1;
22  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
23 
24  /* The platform BIOS needs to ensure the memory ranges of SB800 legacy
25  * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
26  * set to non-posted regions.
27  */
28  PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
29  /* last address before processor local APIC at FEE00000 */
30  PciData = 0x00FEDF00;
31  /* set NP (non-posted) bit */
32  PciData |= 1 << 7;
33  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
34  PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
35  /* lowest NP address is HPET at FED00000 */
36  PciData = (HPET_BASE_ADDRESS >> 8) | 3;
37  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
38 
39  /* Map the remaining PCI hole as posted MMIO */
40  PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
41  PciData = 0x00FECF00; /* last address before non-posted range */
42  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
43  LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
44  MsrReg = (MsrReg >> 8) | 3;
45  PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
46  PciData = (UINT32)MsrReg;
47  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
48 
49  /* Send all IO (0000-FFFF) to southbridge. */
50  PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
51  PciData = 0x0000F000;
52  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
53  PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
54  PciData = 0x00000003;
55  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
56 }
@ AccessWidth32
Access width is 32 bits.
Definition: Amd.h:62
void amd_initcpuio(void)
Definition: fixme.c:11
#define TOP_MEM
Definition: mtrr.h:34
#define HPET_BASE_ADDRESS
Definition: hpet.h:6
The standard header for all AGESA services.
Definition: Amd.h:74