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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Data Structures | |
| struct | dc_cmd_reg |
| struct | dc_com_reg |
| struct | _disp_h_pulse |
| struct | _disp_v_pulse0 |
| struct | _disp_v_pulse2 |
| struct | dc_disp_reg |
| struct | dc_winc_reg |
| struct | dc_win_reg |
| struct | dc_winbuf_reg |
| struct | display_controller |
| struct | tegra_dc |
| struct | tegra_dc_mode |
Macros | |
| #define | DISP_COMMAND_RAISE (1 << 0) |
| #define | DISP_CTRL_MODE_STOP (0 << 5) |
| #define | DISP_CTRL_MODE_C_DISPLAY (1 << 5) |
| #define | DISP_CTRL_MODE_NC_DISPLAY (2 << 5) |
| #define | DISP_COMMAND_RAISE_VECTOR(x) (((x) & 0x1f) << 22) |
| #define | DISP_COMMAND_RAISE_CHANNEL_ID(x) (((x) & 0xf) << 27) |
| #define | PW0_ENABLE BIT(0) |
| #define | PW1_ENABLE BIT(2) |
| #define | PW2_ENABLE BIT(4) |
| #define | PW3_ENABLE BIT(6) |
| #define | PW4_ENABLE BIT(8) |
| #define | PM0_ENABLE BIT(16) |
| #define | PM1_ENABLE BIT(18) |
| #define | SPI_ENABLE BIT(24) |
| #define | HSPI_ENABLE BIT(25) |
| #define | READ_MUX_ASSEMBLY (0 << 0) |
| #define | READ_MUX_ACTIVE (1 << 0) |
| #define | WRITE_MUX_ASSEMBLY (0 << 2) |
| #define | WRITE_MUX_ACTIVE (1 << 2) |
| #define | GENERAL_ACT_REQ BIT(0) |
| #define | WIN_A_ACT_REQ BIT(1) |
| #define | WIN_B_ACT_REQ BIT(2) |
| #define | WIN_C_ACT_REQ BIT(3) |
| #define | WIN_D_ACT_REQ BIT(4) |
| #define | WIN_H_ACT_REQ BIT(5) |
| #define | CURSOR_ACT_REQ BIT(7) |
| #define | GENERAL_UPDATE BIT(8) |
| #define | WIN_A_UPDATE BIT(9) |
| #define | WIN_B_UPDATE BIT(10) |
| #define | WIN_C_UPDATE BIT(11) |
| #define | WIN_D_UPDATE BIT(12) |
| #define | WIN_H_UPDATE BIT(13) |
| #define | CURSOR_UPDATE BIT(15) |
| #define | NC_HOST_TRIG BIT(24) |
| #define | WINDOW_A_SELECT BIT(4) |
| #define | WINDOW_B_SELECT BIT(5) |
| #define | WINDOW_C_SELECT BIT(6) |
| #define | WINDOW_D_SELECT BIT(7) |
| #define | WINDOW_H_SELECT BIT(8) |
| #define | CURSOR_ENABLE BIT(16) |
| #define | SOR_ENABLE BIT(25) |
| #define | TVO_ENABLE BIT(28) |
| #define | DSI_ENABLE BIT(29) |
| #define | HDMI_ENABLE BIT(30) |
| #define | VSYNC_H_POSITION(x) ((x) & 0xfff) |
| #define | SHIFT_CLK_DIVIDER_SHIFT 0 |
| #define | SHIFT_CLK_DIVIDER_MASK (0xff << SHIFT_CLK_DIVIDER_SHIFT) |
| #define | PIXEL_CLK_DIVIDER_SHIFT 8 |
| #define | PIXEL_CLK_DIVIDER_MSK (0xf << PIXEL_CLK_DIVIDER_SHIFT) |
| #define | SHIFT_CLK_DIVIDER(x) (((x) - 1) * 2) |
| #define | H_DIRECTION_DECREMENT(x) ((x) << 0) |
| #define | V_DIRECTION_DECREMENT(x) ((x) << 2) |
| #define | WIN_SCAN_COLUMN BIT(4) |
| #define | COLOR_EXPAND BIT(6) |
| #define | H_FILTER_ENABLE(x) ((x) << 8) |
| #define | V_FILTER_ENABLE(x) ((x) << 10) |
| #define | CP_ENABLE BIT(16) |
| #define | CSC_ENABLE BIT(18) |
| #define | DV_ENABLE BIT(20) |
| #define | INTERLACE_ENABLE BIT(23) |
| #define | INTERLACE_DISABLE (0 << 23) |
| #define | WIN_ENABLE BIT(30) |
| #define | DDA_INC(prescaled_size, post_scaled_size) (((prescaled_size) - 1) * 0x1000 / ((post_scaled_size) - 1)) |
| #define | H_DDA_INC(x) (((x) & 0xffff) << 0) |
| #define | V_DDA_INC(x) (((x) & 0xffff) << 16) |
Functions | |
| check_member (dc_cmd_reg, reg_act_ctrl, 0x43 *4) | |
| check_member (dc_com_reg, crc_checksum_latched,(0x329 - 0x300) *4) | |
| check_member (dc_disp_reg, blend_background_color,(0x4e4 - 0x400) *4) | |
| check_member (dc_winc_reg, v_filter_p,(0x619 - 0x500) *4) | |
| check_member (dc_win_reg, blend_alpha_1bit,(0x719 - 0x700) *4) | |
| check_member (dc_winbuf_reg, start_addr_hi,(0x80d - 0x800) *4) | |
| check_member (display_controller, winbuf, 0x800 *4) | |
| unsigned long | READL (void *p) |
| void | WRITEL (unsigned long value, void *p) |
| void | display_startup (struct device *dev) |
| void | dp_init (void *_config) |
| void | dp_enable (void *_dp) |
| unsigned int | fb_base_mb (void) |
| #define DDA_INC | ( | prescaled_size, | |
| post_scaled_size | |||
| ) | (((prescaled_size) - 1) * 0x1000 / ((post_scaled_size) - 1)) |
| #define PIXEL_CLK_DIVIDER_MSK (0xf << PIXEL_CLK_DIVIDER_SHIFT) |
| #define SHIFT_CLK_DIVIDER_MASK (0xff << SHIFT_CLK_DIVIDER_SHIFT) |
| anonymous enum |
| anonymous enum |
| enum dc_disp_h_pulse_pos |
| enum dc_disp_h_pulse_reg |
| enum dc_disp_pp_select |
| enum dc_disp_v_pulse_pos |
| enum dc_winc_filter_p |
| check_member | ( | dc_cmd_reg | , |
| reg_act_ctrl | , | ||
| 0x43 * | 4 | ||
| ) |
| check_member | ( | dc_com_reg | , |
| crc_checksum_latched | , | ||
| (0x329 - 0x300) * | 4 | ||
| ) |
| check_member | ( | dc_disp_reg | , |
| blend_background_color | , | ||
| (0x4e4 - 0x400) * | 4 | ||
| ) |
| check_member | ( | dc_win_reg | , |
| blend_alpha_1bit | , | ||
| (0x719 - 0x700) * | 4 | ||
| ) |
| check_member | ( | dc_winbuf_reg | , |
| start_addr_hi | , | ||
| (0x80d - 0x800) * | 4 | ||
| ) |
| check_member | ( | dc_winc_reg | , |
| v_filter_p | , | ||
| (0x619 - 0x500) * | 4 | ||
| ) |
| check_member | ( | display_controller | , |
| winbuf | , | ||
| 0x800 * | 4 | ||
| ) |
Definition at line 189 of file mainboard.c.
References ALIGN_UP, tegra_dc::base, BIOS_ERR, BIOS_INFO, BIOS_SPEW, BIOS_WARNING, device::chip_info, clock_display(), config, tegra_dc::config, dc_data, DCACHE_WRITETHROUGH, DIV_ROUND_UP, dp_enable(), dp_init(), dsi_display_startup(), fb_add_framebuffer_info(), fb_base_mb(), gpio_output(), memset(), MiB, mmu_config_range(), NV_PWM_CSR_ENABLE_SHIFT, NV_PWM_CSR_PULSE_WIDTH_SHIFT, tegra_dc::out, printk, TEGRA_ARM_DISPLAYA, tegra_dc_init(), TEGRA_PWM_BASE, udelay(), update_display_mode(), update_window(), and WRITEL().
Referenced by mainboard_init().
Definition at line 1394 of file dp.c.
References BIOS_ERR, config, tegra_dc::config, tegra_dc_dp_data::dc, soc_nvidia_tegra210_config::dp, DP_POWER_ON_MAX_TRIES, DPAUX_DP_AUXSTAT, DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED, tegra_dc_dp_data::enabled, tegra_dc_dp_data::link_cfg, NV_DPCD_REV, NV_DPCD_SET_POWER, NV_DPCD_SET_POWER_VAL_D0_NORMAL, printk, retry, tegra_dc_dp_data::revision, tegra_dc_dp_data::sor, tegra_dc_dp_check_sink(), tegra_dc_dp_dpcd_read(), tegra_dc_dp_dpcd_write(), tegra_dc_dp_explore_link_cfg(), tegra_dc_dp_init_max_link_cfg(), tegra_dc_dpaux_enable(), tegra_dc_sor_attach(), tegra_dc_sor_enable_dp(), tegra_dc_sor_power_down_unused_lanes(), tegra_dc_sor_set_panel_power(), tegra_dc_sor_set_power_state(), tegra_dp_hpd_config(), tegra_dp_hpd_plug(), and tegra_dpaux_readl().
Referenced by display_startup(), and dp_display_startup().
Definition at line 1344 of file dp.c.
References tegra_dc_dp_data::aux_base, tegra_dc_sor_data::base, config, tegra_dc_dp_data::dc, tegra_dc_sor_data::dc, dp_data, tegra_dc_dp_data::enabled, tegra_dc_dp_link_config::is_valid, tegra_dc_dp_data::link_cfg, tegra_dc_sor_data::link_cfg, tegra_dc::out, tegra_dc_sor_data::pmc_base, tegra_dc_sor_data::portnum, tegra_dc_sor_data::power_is_up, tegra_dc_dp_data::sor, TEGRA_ARM_DPAUX, TEGRA_ARM_SOR, tegra_dp_update_config(), and TEGRA_PMC_BASE.
Referenced by display_startup(), and dp_display_startup().
Definition at line 190 of file display.c.
References FB_SIZE_MB, and sdram_max_addressable_mb().
Referenced by display_startup(), and soc_read_resources().
Definition at line 24 of file display.c.
References BIOS_SPEW, dump, printk, read32(), and value.
Referenced by tegra_dc_detach(), tegra_dc_poll_register(), tegra_dc_sor_attach(), tegra_dc_sor_disable_win_short_raster(), tegra_dc_sor_enable_dc(), tegra_dc_sor_enable_sor(), tegra_dc_sor_io_set_dpd(), tegra_dc_sor_restore_win_and_raster(), tegra_dpaux_readl(), tegra_sor_readl(), and update_window().
Definition at line 41 of file display.c.
References BIOS_SPEW, dump, printk, value, and write32().
Referenced by display_startup(), dp_display_startup(), tegra_dc_detach(), tegra_dc_init(), tegra_dc_sor_attach(), tegra_dc_sor_disable_win_short_raster(), tegra_dc_sor_enable_dc(), tegra_dc_sor_enable_sor(), tegra_dc_sor_io_set_dpd(), tegra_dc_sor_restore_win_and_raster(), tegra_dpaux_writel(), tegra_sor_writel(), update_display_mode(), update_display_shift_clock_divider(), and update_window().
1.9.1