Macros
#define	XHCI_PWR_CTL_STS 0x74

#define	XHCI_PWR_CTL_SET_MASK 0x3

#define	XHCI_PWR_CTL_SET_D0 0x0

#define	XHCI_PWR_CTL_SET_D3 0x3

#define	XHCI_PWR_CTL_ENABLE_PME (1 << 8)

#define	XHCI_PWR_CTL_STATUS_PME (1 << 15)

#define	XHCI_USB2PR 0xd0

#define	XHCI_USB2PRM 0xd4

#define	XHCI_USB2PR_HCSEL 0x7fff

#define	XHCI_USB3PR 0xd8

#define	XHCI_USB3PR_SSEN 0x3f

#define	XHCI_USB3PRM 0xdc

#define	XHCI_USB3FUS 0xe0

#define	XHCI_USB3FUS_SS_MASK 3

#define	XHCI_USB3FUS_SS_SHIFT 3

#define	XHCI_USB3PDO 0xe8

#define	XHCI_USB3_PORTSC(port) (0x530 + (port * 0x10))

#define	XHCI_USB3_PORTSC_CHST (0x7f << 17)

#define	XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */

#define	XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */

#define	XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */

#define	XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */

#define	XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */

#define	XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */

#define	XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */

#define	XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */

#define	XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */

#define	XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */

#define	XHCI_PLSR_POLLING (7 << 5) /* Port is polling */

#define	XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */

Functions
void	usb_xhci_sleep_prepare (pci_devfn_t dev, u8 slp_typ)

Macro Definition Documentation

◆ XHCI_PLSR_DISABLED

#define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */

Definition at line 35 of file xhci.h.

◆ XHCI_PLSR_POLLING

#define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */

Definition at line 37 of file xhci.h.

◆ XHCI_PLSR_RXDETECT

#define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */

Definition at line 36 of file xhci.h.

◆ XHCI_PLSW_ENABLE

#define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */

Definition at line 38 of file xhci.h.

◆ XHCI_PWR_CTL_ENABLE_PME

#define XHCI_PWR_CTL_ENABLE_PME (1 << 8)

Definition at line 11 of file xhci.h.

◆ XHCI_PWR_CTL_SET_D0

#define XHCI_PWR_CTL_SET_D0 0x0

Definition at line 9 of file xhci.h.

◆ XHCI_PWR_CTL_SET_D3

#define XHCI_PWR_CTL_SET_D3 0x3

Definition at line 10 of file xhci.h.

◆ XHCI_PWR_CTL_SET_MASK

#define XHCI_PWR_CTL_SET_MASK 0x3

Definition at line 8 of file xhci.h.

◆ XHCI_PWR_CTL_STATUS_PME

#define XHCI_PWR_CTL_STATUS_PME (1 << 15)

Definition at line 12 of file xhci.h.

◆ XHCI_PWR_CTL_STS

#define XHCI_PWR_CTL_STS 0x74

Definition at line 7 of file xhci.h.

◆ XHCI_USB2PR

#define XHCI_USB2PR 0xd0

Definition at line 13 of file xhci.h.

◆ XHCI_USB2PR_HCSEL

#define XHCI_USB2PR_HCSEL 0x7fff

Definition at line 15 of file xhci.h.

◆ XHCI_USB2PRM

#define XHCI_USB2PRM 0xd4

Definition at line 14 of file xhci.h.

◆ XHCI_USB3_PORTSC

#define XHCI_USB3_PORTSC ( port ) (0x530 + (port * 0x10))

Definition at line 25 of file xhci.h.

◆ XHCI_USB3_PORTSC_CHST

#define XHCI_USB3_PORTSC_CHST (0x7f << 17)

Definition at line 26 of file xhci.h.

◆ XHCI_USB3_PORTSC_LWS

#define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */

Definition at line 31 of file xhci.h.

◆ XHCI_USB3_PORTSC_PED

#define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */

Definition at line 32 of file xhci.h.

◆ XHCI_USB3_PORTSC_PLS

#define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */

Definition at line 34 of file xhci.h.

◆ XHCI_USB3_PORTSC_WCE

#define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */

Definition at line 27 of file xhci.h.

◆ XHCI_USB3_PORTSC_WDE

#define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */

Definition at line 28 of file xhci.h.

◆ XHCI_USB3_PORTSC_WOE

#define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */

Definition at line 29 of file xhci.h.

◆ XHCI_USB3_PORTSC_WPR

#define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */

Definition at line 33 of file xhci.h.

◆ XHCI_USB3_PORTSC_WRC

#define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */

Definition at line 30 of file xhci.h.

◆ XHCI_USB3FUS

#define XHCI_USB3FUS 0xe0

Definition at line 19 of file xhci.h.

◆ XHCI_USB3FUS_SS_MASK

#define XHCI_USB3FUS_SS_MASK 3

Definition at line 20 of file xhci.h.

◆ XHCI_USB3FUS_SS_SHIFT

#define XHCI_USB3FUS_SS_SHIFT 3

Definition at line 21 of file xhci.h.

◆ XHCI_USB3PDO

#define XHCI_USB3PDO 0xe8

Definition at line 22 of file xhci.h.

◆ XHCI_USB3PR

#define XHCI_USB3PR 0xd8

Definition at line 16 of file xhci.h.

◆ XHCI_USB3PR_SSEN

#define XHCI_USB3PR_SSEN 0x3f

Definition at line 17 of file xhci.h.

◆ XHCI_USB3PRM

#define XHCI_USB3PRM 0xdc

Definition at line 18 of file xhci.h.

Function Documentation

◆ usb_xhci_sleep_prepare()

void usb_xhci_sleep_prepare	(	pci_devfn_t	dev,
		u8	slp_typ
	)

Referenced by southbridge_smi_sleep().

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Macros

Functions