coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
nvs.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef SOUTHBRIDGE_INTEL_BD82X6X_NVS_H
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#define SOUTHBRIDGE_INTEL_BD82X6X_NVS_H
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#include <
stdint.h
>
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struct
__packed
global_nvs
{
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/* Miscellaneous */
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u16
unused_was_osys;
/* 0x00 - Operating System */
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u8
smif;
/* 0x02 - SMI function call ("TRAP") */
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u8
unused_was_prm0;
/* 0x03 - SMI function call parameter */
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u8
unused_was_prm1;
/* 0x04 - SMI function call parameter */
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u8
scif;
/* 0x05 - SCI function call (via _L00) */
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u8
unused_was_prm2;
/* 0x06 - SCI function call parameter */
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u8
unused_was_prm3;
/* 0x07 - SCI function call parameter */
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u8
unused_was_lckf;
/* 0x08 - Global Lock function for EC */
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u8
unused_was_prm4;
/* 0x09 - Lock function parameter */
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u8
unused_was_prm5;
/* 0x0a - Lock function parameter */
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u32
p80d;
/* 0x0b - Debug port (IO 0x80) value */
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u8
lids;
/* 0x0f - LID state (open = 1) */
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u8
unused_was_pwrs;
/* 0x10 - Power state (AC = 1) */
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/* Thermal policy */
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u8
tlvl;
/* 0x11 - Throttle Level Limit */
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u8
flvl;
/* 0x12 - Current FAN Level */
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u8
tcrt;
/* 0x13 - Critical Threshold */
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u8
tpsv;
/* 0x14 - Passive Threshold */
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u8
tmax;
/* 0x15 - CPU Tj_max */
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u8
f0of
;
/* 0x16 - FAN 0 OFF Threshold */
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u8
f0on
;
/* 0x17 - FAN 0 ON Threshold */
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u8
f0pw
;
/* 0x18 - FAN 0 PWM value */
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u8
f1of
;
/* 0x19 - FAN 1 OFF Threshold */
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u8
f1on
;
/* 0x1a - FAN 1 ON Threshold */
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u8
f1pw
;
/* 0x1b - FAN 1 PWM value */
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u8
f2of
;
/* 0x1c - FAN 2 OFF Threshold */
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u8
f2on
;
/* 0x1d - FAN 2 ON Threshold */
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u8
f2pw
;
/* 0x1e - FAN 2 PWM value */
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u8
f3of
;
/* 0x1f - FAN 3 OFF Threshold */
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u8
f3on
;
/* 0x20 - FAN 3 ON Threshold */
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u8
f3pw
;
/* 0x21 - FAN 3 PWM value */
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u8
f4of
;
/* 0x22 - FAN 4 OFF Threshold */
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u8
f4on
;
/* 0x23 - FAN 4 ON Threshold */
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u8
f4pw
;
/* 0x24 - FAN 4 PWM value */
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u8
tmps;
/* 0x25 - Temperature Sensor ID */
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u8
rsvd3[2];
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/* Processor Identification */
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u8
unused_was_apic
;
/* 0x28 - APIC enabled */
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u8
unused_was_mpen
;
/* 0x29 - MP capable/enabled */
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u8
pcp0
;
/* 0x2a - PDC CPU/CORE 0 */
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u8
pcp1
;
/* 0x2b - PDC CPU/CORE 1 */
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u8
ppcm;
/* 0x2c - Max. PPC state */
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u8
unused_was_pcnt;
/* 0x2d - Processor Count */
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u8
rsvd4[4];
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/* Super I/O & CMOS config */
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u8
natp
;
/* 0x32 - SIO type */
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u8
s5u0;
/* 0x33 - Enable USB0 in S5 */
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u8
s5u1;
/* 0x34 - Enable USB1 in S5 */
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u8
s3u0;
/* 0x35 - Enable USB0 in S3 */
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u8
s3u1;
/* 0x36 - Enable USB1 in S3 */
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u8
s33g;
/* 0x37 - Enable S3 in 3G */
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u32
obsolete_cmem;
/* 0x38 - CBMEM TOC */
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/* Integrated Graphics Device */
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u8
igds
;
/* 0x3c - IGD state */
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u8
tlst
;
/* 0x3d - Display Toggle List Pointer */
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u8
cadl
;
/* 0x3e - currently attached devices */
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u8
padl
;
/* 0x3f - previously attached devices */
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u8
rsvd5[36];
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/* Backlight Control */
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u8
blcs
;
/* 0x64 - Backlight Control possible */
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u8
brtl
;
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u8
odds
;
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u8
rsvd6[0x7];
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/* Ambient Light Sensors*/
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u8
alse
;
/* 0x6e - ALS enable */
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u8
alaf
;
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u8
llow
;
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u8
lhih
;
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u8
rsvd7[0x6];
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/* Extended Mobile Access */
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u8
emae
;
/* 0x78 - EMA enable */
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u16
emap
;
/* 0x79 - EMA pointer */
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u16
emal
;
/* 0x7a - EMA Length */
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u8
rsvd8[0x5];
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/* MEF */
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u8
mefe
;
/* 0x82 - MEF enable */
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u8
rsvd9[0x9];
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/* TPM support */
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u8
tpmp;
/* 0x8c - TPM */
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u8
tpme
;
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u8
rsvd10[8];
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/* SATA */
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u8
gtf0[7];
/* 0x96 - GTF task file buffer for port 0 */
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u8
gtf1[7];
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u8
gtf2[7];
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u8
idem
;
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u8
idet
;
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u8
rsvd11[6];
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/* XHCI */
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u8
xhci
;
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/* Required for future unified acpi_save_wake_source. */
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u32
pm1i;
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u32
gpei;
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u8
rsvd12[57];
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u8
tpiq
;
/* 0xf5 - trackpad IRQ value */
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u32
cbmc;
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};
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#endif
/* SOUTHBRIDGE_INTEL_BD82X6X_NVS_H */
stdint.h
u32
uint32_t u32
Definition:
stdint.h:51
u16
uint16_t u16
Definition:
stdint.h:48
u8
uint8_t u8
Definition:
stdint.h:45
__packed
Definition:
x86.c:23
global_nvs
Definition:
nvs.h:14
global_nvs::llow
u8 llow
Definition:
nvs.h:76
global_nvs::natp
u8 natp
Definition:
nvs.h:55
global_nvs::emae
u8 emae
Definition:
nvs.h:80
global_nvs::cadl
u8 cadl
Definition:
nvs.h:65
global_nvs::f3of
u8 f3of
Definition:
nvs.h:38
global_nvs::unused_was_mpen
u8 unused_was_mpen
Definition:
nvs.h:48
global_nvs::padl
u8 padl
Definition:
nvs.h:66
global_nvs::pcp0
u8 pcp0
Definition:
nvs.h:49
global_nvs::f1of
u8 f1of
Definition:
nvs.h:32
global_nvs::f4on
u8 f4on
Definition:
nvs.h:42
global_nvs::f2pw
u8 f2pw
Definition:
nvs.h:37
global_nvs::lhih
u8 lhih
Definition:
nvs.h:77
global_nvs::f2on
u8 f2on
Definition:
nvs.h:36
global_nvs::blcs
u8 blcs
Definition:
nvs.h:69
global_nvs::emal
u16 emal
Definition:
nvs.h:82
global_nvs::tlst
u8 tlst
Definition:
nvs.h:64
global_nvs::pcp1
u8 pcp1
Definition:
nvs.h:50
global_nvs::f2of
u8 f2of
Definition:
nvs.h:35
global_nvs::unused_was_apic
u8 unused_was_apic
Definition:
nvs.h:47
global_nvs::tpiq
u8 tpiq
Definition:
nvs.h:106
global_nvs::f0on
u8 f0on
Definition:
nvs.h:30
global_nvs::f4of
u8 f4of
Definition:
nvs.h:41
global_nvs::odds
u8 odds
Definition:
nvs.h:71
global_nvs::f3pw
u8 f3pw
Definition:
nvs.h:40
global_nvs::f3on
u8 f3on
Definition:
nvs.h:39
global_nvs::alaf
u8 alaf
Definition:
nvs.h:75
global_nvs::f1pw
u8 f1pw
Definition:
nvs.h:34
global_nvs::f1on
u8 f1on
Definition:
nvs.h:33
global_nvs::igds
u8 igds
Definition:
nvs.h:63
global_nvs::tpme
u8 tpme
Definition:
nvs.h:89
global_nvs::f0of
u8 f0of
Definition:
nvs.h:29
global_nvs::f4pw
u8 f4pw
Definition:
nvs.h:43
global_nvs::alse
u8 alse
Definition:
nvs.h:74
global_nvs::idet
u8 idet
Definition:
nvs.h:96
global_nvs::idem
u8 idem
Definition:
nvs.h:95
global_nvs::emap
u16 emap
Definition:
nvs.h:81
global_nvs::xhci
u8 xhci
Definition:
nvs.h:99
global_nvs::brtl
u8 brtl
Definition:
nvs.h:70
global_nvs::f0pw
u8 f0pw
Definition:
nvs.h:31
global_nvs::mefe
u8 mefe
Definition:
nvs.h:85
src
southbridge
intel
bd82x6x
include
soc
nvs.h
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