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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <commonlib/helpers.h>
#include <device/mmio.h>
#include <device/pci_rom.h>
#include <device/resource.h>
#include <drivers/intel/gma/i915.h>
#include <drivers/intel/gma/i915_reg.h>
#include <intelblocks/graphics.h>
#include <soc/ramstage.h>
#include <soc/systemagent.h>
#include <types.h>
Go to the source code of this file.
Functions | |
void | graphics_soc_panel_init (struct device *dev) |
const struct i915_gpu_controller_info * | intel_igd_get_controller_info (const struct device *device) |
u32 | map_oprom_vendev (u32 vendev) |
Definition at line 14 of file graphics.c.
References i915_gpu_panel_config::backlight_off_delay_ms, i915_gpu_panel_config::backlight_on_delay_ms, i915_gpu_panel_config::backlight_polarity, i915_gpu_panel_config::backlight_pwm_hz, resource::base, base, BLC_PWM_PCH_CTL1, BLC_PWM_PCH_CTL2, BLM_PCH_PWM_ENABLE, config_of(), i915_gpu_panel_config::cycle_delay_ms, DIV_ROUND_UP, i915_gpu_panel_config::down_delay_ms, mmio_res, soc_intel_skylake_config::panel_cfg, PCH_PP_DIVISOR, PCH_PP_OFF_DELAYS, PCH_PP_ON_DELAYS, PCI_BASE_ADDRESS_0, probe_resource(), read32(), SOUTH_CHICKEN1, i915_gpu_panel_config::up_delay_ms, and write32().
const struct i915_gpu_controller_info* intel_igd_get_controller_info | ( | const struct device * | device | ) |
Definition at line 75 of file graphics.c.
References chip, and device::chip_info.
Definition at line 85 of file graphics.c.
References SA_IGD_OPROM_VENDEV.