coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
soc_intel_jasperlake_config Struct Reference

#include <chip.h>

Collaboration diagram for soc_intel_jasperlake_config:
Collaboration graph

Public Types

enum  {
  SaGv_Disabled , SaGv_FixedPoint0 , SaGv_FixedPoint1 , SaGv_FixedPoint2 ,
  SaGv_Enabled
}
 
enum  {
  DEBUG_INTERFACE_RAM = (1 << 0) , DEBUG_INTERFACE_UART_8250IO = (1 << 1) , DEBUG_INTERFACE_USB3 = (1 << 3) , DEBUG_INTERFACE_LPSS_SERIAL_IO = (1 << 4) ,
  DEBUG_INTERFACE_TRACEHUB = (1 << 5)
}
 
enum  { SlewRateFastBy2 = 0 , SlewRateFastBy4 , SlewRateFastBy8 , SlewRateFastBy16 }
 
enum  {
  CD_CLOCK_172_8_MHZ = 1 , CD_CLOCK_180_MHZ = 2 , CD_CLOCK_192_MHZ = 3 , CD_CLOCK_307_MHZ = 4 ,
  CD_CLOCK_312_MHZ = 5 , CD_CLOCK_552_MHZ = 6 , CD_CLOCK_556_8_MHZ = 7
}
 

Data Fields

struct soc_intel_common_config common_soc_config
 
struct soc_power_limits_config power_limits_config
 
uint8_t pmc_gpe0_dw0
 
uint8_t pmc_gpe0_dw1
 
uint8_t pmc_gpe0_dw2
 
uint32_t gen1_dec
 
uint32_t gen2_dec
 
uint32_t gen3_dec
 
uint32_t gen4_dec
 
int s0ix_enable
 
int dptf_enable
 
int deep_s3_enable_ac
 
int deep_s3_enable_dc
 
int deep_s5_enable_ac
 
int deep_s5_enable_dc
 
uint32_t deep_sx_config
 
uint32_t tcc_offset
 
enum soc_intel_jasperlake_config:: { ... }  SaGv
 
uint8_t RMT
 
struct usb2_port_config usb2_ports [16]
 
struct usb3_port_config usb3_ports [10]
 
uint16_t usb2_wake_enable_bitmap
 
uint16_t usb3_wake_enable_bitmap
 
uint8_t xhci_lfps_sampling_offtime_ms
 
uint8_t SataMode
 
uint8_t SataSalpSupport
 
uint8_t SataPortsEnable [8]
 
uint8_t SataPortsDevSlp [8]
 
uint8_t PchHdaDspEnable
 
uint8_t PchHdaAudioLinkHdaEnable
 
uint8_t PchHdaAudioLinkDmicEnable [MAX_HD_AUDIO_DMIC_LINKS]
 
uint8_t PchHdaAudioLinkSspEnable [MAX_HD_AUDIO_SSP_LINKS]
 
uint8_t PchHdaAudioLinkSndwEnable [MAX_HD_AUDIO_SNDW_LINKS]
 
uint8_t PchHdaIDispLinkTmode
 
uint8_t PchHdaIDispLinkFrequency
 
uint8_t PchHdaIDispCodecDisconnect
 
uint8_t PcieRpEnable [CONFIG_MAX_ROOT_PORTS]
 
uint8_t PcieClkSrcUsage [CONFIG_MAX_PCIE_CLOCK_SRC]
 
uint8_t PcieClkSrcClkReq [CONFIG_MAX_PCIE_CLOCK_SRC]
 
uint8_t PcieRpClkReqDetect [CONFIG_MAX_ROOT_PORTS]
 
enum L1_substates_control PcieRpL1Substates [CONFIG_MAX_ROOT_PORTS]
 
struct pcie_modphy_config pcie_mp_cfg [CONFIG_MAX_ROOT_PORTS]
 
uint8_t SmbusEnable
 
uint8_t ScsEmmcHs400Enabled
 
uint8_t SdCardPowerEnableActiveHigh
 
uint16_t ImonSlope
 
uint16_t ImonOffset
 
uint8_t SkipExtGfxScan
 
uint8_t eist_enable
 
uint8_t enable_c6dram
 
uint8_t SerialIoI2cMode [CONFIG_SOC_INTEL_I2C_DEV_MAX]
 
uint8_t SerialIoGSpiMode [CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]
 
uint8_t SerialIoUartMode [CONFIG_SOC_INTEL_UART_DEV_MAX]
 
uint8_t SerialIoGSpiCsMode [CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]
 
uint8_t SerialIoGSpiCsState [CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]
 
uint8_t TraceHubMode
 
enum soc_intel_jasperlake_config:: { ... }  debug_interface_flag
 
unsigned int sdcard_cd_gpio
 
uint8_t pch_isclk
 
bool CnviBtAudioOffload
 
uint8_t TcssXhciEn
 
uint8_t TcssXdciEn
 
uint8_t gpio_override_pm
 
uint8_t gpio_pm [TOTAL_GPIO_COMM]
 
uint8_t DdiPortAConfig
 
uint8_t DdiPortBConfig
 
uint8_t DdiPortAHpd
 
uint8_t DdiPortBHpd
 
uint8_t DdiPortCHpd
 
uint8_t DdiPort1Hpd
 
uint8_t DdiPort2Hpd
 
uint8_t DdiPort3Hpd
 
uint8_t DdiPort4Hpd
 
uint8_t DdiPortADdc
 
uint8_t DdiPortBDdc
 
uint8_t DdiPortCDdc
 
uint8_t DdiPort1Ddc
 
uint8_t DdiPort2Ddc
 
uint8_t DdiPort3Ddc
 
uint8_t DdiPort4Ddc
 
uint8_t HybridStorageMode
 
uint8_t cpu_ratio_override
 
uint8_t SkipCpuReplacementCheck
 
uint8_t PchPmSlpS3MinAssert
 
uint8_t PchPmSlpS4MinAssert
 
uint8_t PchPmSlpSusMinAssert
 
uint8_t PchPmSlpAMinAssert
 
uint8_t PchPmPwrCycDur
 
uint16_t FivrRfiFrequency
 
uint8_t FivrSpreadSpectrum
 
uint8_t FastPkgCRampDisable
 
enum soc_intel_jasperlake_config:: { ... }  SlowSlewRate
 
uint8_t AcousticNoiseMitigation
 
uint8_t PreWake
 
uint8_t RampUp
 
uint8_t RampDown
 
bool disable_external_bypass_vr
 
enum soc_intel_jasperlake_config:: { ... }  cd_clock
 
bool cnvi_reduce_s0ix_pwr_usage
 

Detailed Description

Definition at line 26 of file chip.h.

Member Enumeration Documentation

◆ anonymous enum

anonymous enum
Enumerator
SaGv_Disabled 
SaGv_FixedPoint0 
SaGv_FixedPoint1 
SaGv_FixedPoint2 
SaGv_Enabled 

Definition at line 70 of file chip.h.

◆ anonymous enum

anonymous enum
Enumerator
DEBUG_INTERFACE_RAM 
DEBUG_INTERFACE_UART_8250IO 
DEBUG_INTERFACE_USB3 
DEBUG_INTERFACE_LPSS_SERIAL_IO 
DEBUG_INTERFACE_TRACEHUB 

Definition at line 182 of file chip.h.

◆ anonymous enum

anonymous enum
Enumerator
SlewRateFastBy2 
SlewRateFastBy4 
SlewRateFastBy8 
SlewRateFastBy16 

Definition at line 355 of file chip.h.

◆ anonymous enum

anonymous enum
Enumerator
CD_CLOCK_172_8_MHZ 
CD_CLOCK_180_MHZ 
CD_CLOCK_192_MHZ 
CD_CLOCK_307_MHZ 
CD_CLOCK_312_MHZ 
CD_CLOCK_552_MHZ 
CD_CLOCK_556_8_MHZ 

Definition at line 412 of file chip.h.

Field Documentation

◆ AcousticNoiseMitigation

uint8_t soc_intel_jasperlake_config::AcousticNoiseMitigation

Definition at line 366 of file chip.h.

◆ 

enum { ... } soc_intel_jasperlake_config::cd_clock

◆ cnvi_reduce_s0ix_pwr_usage

bool soc_intel_jasperlake_config::cnvi_reduce_s0ix_pwr_usage

Definition at line 434 of file chip.h.

◆ CnviBtAudioOffload

bool soc_intel_jasperlake_config::CnviBtAudioOffload

Definition at line 197 of file chip.h.

◆ common_soc_config

struct soc_intel_common_config soc_intel_jasperlake_config::common_soc_config

Definition at line 1 of file chip.h.

◆ cpu_ratio_override

uint8_t soc_intel_jasperlake_config::cpu_ratio_override

Definition at line 262 of file chip.h.

◆ DdiPort1Ddc

uint8_t soc_intel_jasperlake_config::DdiPort1Ddc

Definition at line 243 of file chip.h.

◆ DdiPort1Hpd

uint8_t soc_intel_jasperlake_config::DdiPort1Hpd

Definition at line 234 of file chip.h.

◆ DdiPort2Ddc

uint8_t soc_intel_jasperlake_config::DdiPort2Ddc

Definition at line 244 of file chip.h.

◆ DdiPort2Hpd

uint8_t soc_intel_jasperlake_config::DdiPort2Hpd

Definition at line 235 of file chip.h.

◆ DdiPort3Ddc

uint8_t soc_intel_jasperlake_config::DdiPort3Ddc

Definition at line 245 of file chip.h.

◆ DdiPort3Hpd

uint8_t soc_intel_jasperlake_config::DdiPort3Hpd

Definition at line 236 of file chip.h.

◆ DdiPort4Ddc

uint8_t soc_intel_jasperlake_config::DdiPort4Ddc

Definition at line 246 of file chip.h.

◆ DdiPort4Hpd

uint8_t soc_intel_jasperlake_config::DdiPort4Hpd

Definition at line 237 of file chip.h.

◆ DdiPortAConfig

uint8_t soc_intel_jasperlake_config::DdiPortAConfig

Definition at line 227 of file chip.h.

◆ DdiPortADdc

uint8_t soc_intel_jasperlake_config::DdiPortADdc

Definition at line 240 of file chip.h.

◆ DdiPortAHpd

uint8_t soc_intel_jasperlake_config::DdiPortAHpd

Definition at line 231 of file chip.h.

◆ DdiPortBConfig

uint8_t soc_intel_jasperlake_config::DdiPortBConfig

Definition at line 228 of file chip.h.

◆ DdiPortBDdc

uint8_t soc_intel_jasperlake_config::DdiPortBDdc

Definition at line 241 of file chip.h.

◆ DdiPortBHpd

uint8_t soc_intel_jasperlake_config::DdiPortBHpd

Definition at line 232 of file chip.h.

◆ DdiPortCDdc

uint8_t soc_intel_jasperlake_config::DdiPortCDdc

Definition at line 242 of file chip.h.

◆ DdiPortCHpd

uint8_t soc_intel_jasperlake_config::DdiPortCHpd

Definition at line 233 of file chip.h.

◆ 

enum { ... } soc_intel_jasperlake_config::debug_interface_flag

◆ deep_s3_enable_ac

int soc_intel_jasperlake_config::deep_s3_enable_ac

Definition at line 52 of file chip.h.

◆ deep_s3_enable_dc

int soc_intel_jasperlake_config::deep_s3_enable_dc

Definition at line 53 of file chip.h.

◆ deep_s5_enable_ac

int soc_intel_jasperlake_config::deep_s5_enable_ac

Definition at line 54 of file chip.h.

◆ deep_s5_enable_dc

int soc_intel_jasperlake_config::deep_s5_enable_dc

Definition at line 55 of file chip.h.

◆ deep_sx_config

uint32_t soc_intel_jasperlake_config::deep_sx_config

Definition at line 61 of file chip.h.

◆ disable_external_bypass_vr

bool soc_intel_jasperlake_config::disable_external_bypass_vr

Definition at line 402 of file chip.h.

Referenced by ext_vr_update().

◆ dptf_enable

int soc_intel_jasperlake_config::dptf_enable

Definition at line 49 of file chip.h.

◆ eist_enable

uint8_t soc_intel_jasperlake_config::eist_enable

Definition at line 146 of file chip.h.

◆ enable_c6dram

uint8_t soc_intel_jasperlake_config::enable_c6dram

Definition at line 149 of file chip.h.

◆ FastPkgCRampDisable

uint8_t soc_intel_jasperlake_config::FastPkgCRampDisable

Definition at line 348 of file chip.h.

◆ FivrRfiFrequency

uint16_t soc_intel_jasperlake_config::FivrRfiFrequency

Definition at line 333 of file chip.h.

◆ FivrSpreadSpectrum

uint8_t soc_intel_jasperlake_config::FivrSpreadSpectrum

Definition at line 341 of file chip.h.

◆ gen1_dec

uint32_t soc_intel_jasperlake_config::gen1_dec

Definition at line 41 of file chip.h.

◆ gen2_dec

uint32_t soc_intel_jasperlake_config::gen2_dec

Definition at line 42 of file chip.h.

◆ gen3_dec

uint32_t soc_intel_jasperlake_config::gen3_dec

Definition at line 43 of file chip.h.

◆ gen4_dec

uint32_t soc_intel_jasperlake_config::gen4_dec

Definition at line 44 of file chip.h.

◆ gpio_override_pm

uint8_t soc_intel_jasperlake_config::gpio_override_pm

Definition at line 208 of file chip.h.

Referenced by mainboard_update_soc_chip_config().

◆ gpio_pm

uint8_t soc_intel_jasperlake_config::gpio_pm[TOTAL_GPIO_COMM]

Definition at line 220 of file chip.h.

Referenced by mainboard_update_soc_chip_config().

◆ HybridStorageMode

uint8_t soc_intel_jasperlake_config::HybridStorageMode

Definition at line 251 of file chip.h.

◆ ImonOffset

uint16_t soc_intel_jasperlake_config::ImonOffset

Definition at line 140 of file chip.h.

◆ ImonSlope

uint16_t soc_intel_jasperlake_config::ImonSlope

Definition at line 139 of file chip.h.

◆ pch_isclk

uint8_t soc_intel_jasperlake_config::pch_isclk

Definition at line 194 of file chip.h.

◆ PchHdaAudioLinkDmicEnable

uint8_t soc_intel_jasperlake_config::PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS]

Definition at line 103 of file chip.h.

◆ PchHdaAudioLinkHdaEnable

uint8_t soc_intel_jasperlake_config::PchHdaAudioLinkHdaEnable

Definition at line 102 of file chip.h.

◆ PchHdaAudioLinkSndwEnable

uint8_t soc_intel_jasperlake_config::PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS]

Definition at line 105 of file chip.h.

◆ PchHdaAudioLinkSspEnable

uint8_t soc_intel_jasperlake_config::PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS]

Definition at line 104 of file chip.h.

◆ PchHdaDspEnable

uint8_t soc_intel_jasperlake_config::PchHdaDspEnable

Definition at line 101 of file chip.h.

◆ PchHdaIDispCodecDisconnect

uint8_t soc_intel_jasperlake_config::PchHdaIDispCodecDisconnect

Definition at line 108 of file chip.h.

◆ PchHdaIDispLinkFrequency

uint8_t soc_intel_jasperlake_config::PchHdaIDispLinkFrequency

Definition at line 107 of file chip.h.

◆ PchHdaIDispLinkTmode

uint8_t soc_intel_jasperlake_config::PchHdaIDispLinkTmode

Definition at line 106 of file chip.h.

◆ PchPmPwrCycDur

uint8_t soc_intel_jasperlake_config::PchPmPwrCycDur

Definition at line 323 of file chip.h.

◆ PchPmSlpAMinAssert

uint8_t soc_intel_jasperlake_config::PchPmSlpAMinAssert

Definition at line 306 of file chip.h.

◆ PchPmSlpS3MinAssert

uint8_t soc_intel_jasperlake_config::PchPmSlpS3MinAssert

Definition at line 279 of file chip.h.

◆ PchPmSlpS4MinAssert

uint8_t soc_intel_jasperlake_config::PchPmSlpS4MinAssert

Definition at line 288 of file chip.h.

◆ PchPmSlpSusMinAssert

uint8_t soc_intel_jasperlake_config::PchPmSlpSusMinAssert

Definition at line 297 of file chip.h.

◆ pcie_mp_cfg

struct pcie_modphy_config soc_intel_jasperlake_config::pcie_mp_cfg[CONFIG_MAX_ROOT_PORTS]

Definition at line 121 of file chip.h.

◆ PcieClkSrcClkReq

uint8_t soc_intel_jasperlake_config::PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_SRC]

Definition at line 118 of file chip.h.

◆ PcieClkSrcUsage

uint8_t soc_intel_jasperlake_config::PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCK_SRC]

Definition at line 115 of file chip.h.

◆ PcieRpClkReqDetect

uint8_t soc_intel_jasperlake_config::PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]

Definition at line 121 of file chip.h.

◆ PcieRpEnable

uint8_t soc_intel_jasperlake_config::PcieRpEnable[CONFIG_MAX_ROOT_PORTS]

Definition at line 111 of file chip.h.

◆ PcieRpL1Substates

enum L1_substates_control soc_intel_jasperlake_config::PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]

Definition at line 121 of file chip.h.

◆ pmc_gpe0_dw0

uint8_t soc_intel_jasperlake_config::pmc_gpe0_dw0

Definition at line 36 of file chip.h.

◆ pmc_gpe0_dw1

uint8_t soc_intel_jasperlake_config::pmc_gpe0_dw1

Definition at line 37 of file chip.h.

◆ pmc_gpe0_dw2

uint8_t soc_intel_jasperlake_config::pmc_gpe0_dw2

Definition at line 38 of file chip.h.

◆ power_limits_config

struct soc_power_limits_config soc_intel_jasperlake_config::power_limits_config

Definition at line 1 of file chip.h.

◆ PreWake

uint8_t soc_intel_jasperlake_config::PreWake

Definition at line 374 of file chip.h.

◆ RampDown

uint8_t soc_intel_jasperlake_config::RampDown

Definition at line 390 of file chip.h.

◆ RampUp

uint8_t soc_intel_jasperlake_config::RampUp

Definition at line 382 of file chip.h.

◆ RMT

uint8_t soc_intel_jasperlake_config::RMT

Definition at line 79 of file chip.h.

◆ s0ix_enable

int soc_intel_jasperlake_config::s0ix_enable

Definition at line 47 of file chip.h.

◆ 

enum { ... } soc_intel_jasperlake_config::SaGv

◆ SataMode

uint8_t soc_intel_jasperlake_config::SataMode

Definition at line 95 of file chip.h.

◆ SataPortsDevSlp

uint8_t soc_intel_jasperlake_config::SataPortsDevSlp[8]

Definition at line 98 of file chip.h.

◆ SataPortsEnable

uint8_t soc_intel_jasperlake_config::SataPortsEnable[8]

Definition at line 97 of file chip.h.

◆ SataSalpSupport

uint8_t soc_intel_jasperlake_config::SataSalpSupport

Definition at line 96 of file chip.h.

◆ ScsEmmcHs400Enabled

uint8_t soc_intel_jasperlake_config::ScsEmmcHs400Enabled

Definition at line 133 of file chip.h.

◆ sdcard_cd_gpio

unsigned int soc_intel_jasperlake_config::sdcard_cd_gpio

Definition at line 191 of file chip.h.

◆ SdCardPowerEnableActiveHigh

uint8_t soc_intel_jasperlake_config::SdCardPowerEnableActiveHigh

Definition at line 136 of file chip.h.

◆ SerialIoGSpiCsMode

uint8_t soc_intel_jasperlake_config::SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]

Definition at line 167 of file chip.h.

◆ SerialIoGSpiCsState

uint8_t soc_intel_jasperlake_config::SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]

Definition at line 173 of file chip.h.

◆ SerialIoGSpiMode

uint8_t soc_intel_jasperlake_config::SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]

Definition at line 160 of file chip.h.

◆ SerialIoI2cMode

uint8_t soc_intel_jasperlake_config::SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX]

Definition at line 159 of file chip.h.

◆ SerialIoUartMode

uint8_t soc_intel_jasperlake_config::SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX]

Definition at line 161 of file chip.h.

◆ SkipCpuReplacementCheck

uint8_t soc_intel_jasperlake_config::SkipCpuReplacementCheck

Definition at line 270 of file chip.h.

◆ SkipExtGfxScan

uint8_t soc_intel_jasperlake_config::SkipExtGfxScan

Definition at line 143 of file chip.h.

◆ 

enum { ... } soc_intel_jasperlake_config::SlowSlewRate

◆ SmbusEnable

uint8_t soc_intel_jasperlake_config::SmbusEnable

Definition at line 130 of file chip.h.

◆ tcc_offset

uint32_t soc_intel_jasperlake_config::tcc_offset

Definition at line 64 of file chip.h.

◆ TcssXdciEn

uint8_t soc_intel_jasperlake_config::TcssXdciEn

Definition at line 201 of file chip.h.

◆ TcssXhciEn

uint8_t soc_intel_jasperlake_config::TcssXhciEn

Definition at line 200 of file chip.h.

◆ TraceHubMode

uint8_t soc_intel_jasperlake_config::TraceHubMode

Definition at line 179 of file chip.h.

◆ usb2_ports

struct usb2_port_config soc_intel_jasperlake_config::usb2_ports[16]

Definition at line 79 of file chip.h.

◆ usb2_wake_enable_bitmap

uint16_t soc_intel_jasperlake_config::usb2_wake_enable_bitmap

Definition at line 85 of file chip.h.

◆ usb3_ports

struct usb3_port_config soc_intel_jasperlake_config::usb3_ports[10]

Definition at line 79 of file chip.h.

◆ usb3_wake_enable_bitmap

uint16_t soc_intel_jasperlake_config::usb3_wake_enable_bitmap

Definition at line 87 of file chip.h.

◆ xhci_lfps_sampling_offtime_ms

uint8_t soc_intel_jasperlake_config::xhci_lfps_sampling_offtime_ms

Definition at line 92 of file chip.h.


The documentation for this struct was generated from the following file: