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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <chip.h>
Public Types | |
enum | { SaGv_Disabled , SaGv_FixedPoint0 , SaGv_FixedPoint1 , SaGv_FixedPoint2 , SaGv_Enabled } |
enum | { DEBUG_INTERFACE_RAM = (1 << 0) , DEBUG_INTERFACE_UART_8250IO = (1 << 1) , DEBUG_INTERFACE_USB3 = (1 << 3) , DEBUG_INTERFACE_LPSS_SERIAL_IO = (1 << 4) , DEBUG_INTERFACE_TRACEHUB = (1 << 5) } |
enum | { SlewRateFastBy2 = 0 , SlewRateFastBy4 , SlewRateFastBy8 , SlewRateFastBy16 } |
enum | { CD_CLOCK_172_8_MHZ = 1 , CD_CLOCK_180_MHZ = 2 , CD_CLOCK_192_MHZ = 3 , CD_CLOCK_307_MHZ = 4 , CD_CLOCK_312_MHZ = 5 , CD_CLOCK_552_MHZ = 6 , CD_CLOCK_556_8_MHZ = 7 } |
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enum { ... } soc_intel_jasperlake_config::cd_clock |
struct soc_intel_common_config soc_intel_jasperlake_config::common_soc_config |
enum { ... } soc_intel_jasperlake_config::debug_interface_flag |
bool soc_intel_jasperlake_config::disable_external_bypass_vr |
Definition at line 402 of file chip.h.
Referenced by ext_vr_update().
uint8_t soc_intel_jasperlake_config::gpio_override_pm |
Definition at line 208 of file chip.h.
Referenced by mainboard_update_soc_chip_config().
uint8_t soc_intel_jasperlake_config::gpio_pm[TOTAL_GPIO_COMM] |
Definition at line 220 of file chip.h.
Referenced by mainboard_update_soc_chip_config().
uint8_t soc_intel_jasperlake_config::PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS] |
uint8_t soc_intel_jasperlake_config::PchHdaAudioLinkHdaEnable |
uint8_t soc_intel_jasperlake_config::PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS] |
uint8_t soc_intel_jasperlake_config::PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS] |
uint8_t soc_intel_jasperlake_config::PchHdaIDispCodecDisconnect |
uint8_t soc_intel_jasperlake_config::PchHdaIDispLinkFrequency |
struct pcie_modphy_config soc_intel_jasperlake_config::pcie_mp_cfg[CONFIG_MAX_ROOT_PORTS] |
uint8_t soc_intel_jasperlake_config::PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_SRC] |
uint8_t soc_intel_jasperlake_config::PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCK_SRC] |
uint8_t soc_intel_jasperlake_config::PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS] |
uint8_t soc_intel_jasperlake_config::PcieRpEnable[CONFIG_MAX_ROOT_PORTS] |
enum L1_substates_control soc_intel_jasperlake_config::PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS] |
struct soc_power_limits_config soc_intel_jasperlake_config::power_limits_config |
enum { ... } soc_intel_jasperlake_config::SaGv |
uint8_t soc_intel_jasperlake_config::SdCardPowerEnableActiveHigh |
uint8_t soc_intel_jasperlake_config::SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX] |
uint8_t soc_intel_jasperlake_config::SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX] |
uint8_t soc_intel_jasperlake_config::SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX] |
uint8_t soc_intel_jasperlake_config::SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX] |
uint8_t soc_intel_jasperlake_config::SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX] |
enum { ... } soc_intel_jasperlake_config::SlowSlewRate |
struct usb2_port_config soc_intel_jasperlake_config::usb2_ports[16] |
struct usb3_port_config soc_intel_jasperlake_config::usb3_ports[10] |
uint8_t soc_intel_jasperlake_config::xhci_lfps_sampling_offtime_ms |