coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Enumerations | |
enum | { POWER_RESET_POR = 0 , POWER_RESET_WATCHDOG = 1 , POWER_RESET_SENSOR = 2 , POWER_RESET_SW_MAIN = 3 , POWER_RESET_LP0 = 4 } |
Functions | |
void | power_enable_and_ungate_cpu (void) |
int | power_reset_status (void) |
void | ram_repair (void) |
anonymous enum |
Definition at line 52 of file power.c.
References tegra_pmc_regs::cntrl, tegra_pmc_regs::cpupwrgood_timer, pmc, PMC_CNTRL_CPUPWRREQ_OE, PMC_CNTRL_CPUPWRREQ_POLARITY, POWER_PARTID_C0NC, POWER_PARTID_CE0, POWER_PARTID_CRAIL, power_ungate_partition(), read32(), TEGRA_PCLK_KHZ, and write32().
Referenced by run_next_stage().
int power_reset_status | ( | void | ) |
Definition at line 74 of file power.c.
References pmc, read32(), and tegra_pmc_regs::rst_status.
Referenced by romstage().
Definition at line 444 of file tegra_lp0_resume.c.
References flow, flow_ctlr_ram_repair_cluster1_ptr, flow_ctlr_ram_repair_ptr, flow_ctlr::ram_repair, flow_ctlr::ram_repair_cluster1, RAM_REPAIR_REQ, RAM_REPAIR_STS, read32(), and setbits32().
Referenced by lp0_resume(), and run_next_stage().