3 #ifndef __SOC_NVIDIA_TEGRA124_CLOCK_H__
4 #define __SOC_NVIDIA_TEGRA124_CLOCK_H__
9 #include <soc/clk_rst.h>
163 #define CLOCK_PLL_STABLE_DELAY_US 300
165 #define IO_STABILIZATION_DELAY (2)
188 #define CLK_DIVIDER(REF, FREQ) (DIV_ROUND_UP(((REF) * 2), (FREQ)) - 2)
207 #define CLK_FREQUENCY(REF, REG) (((REF) * 2) / ((REG) + 2))
215 if (div & ~div_mask) {
223 #define clock_configure_irregular_source(device, src, freq, src_id) \
224 _clock_set_div(&clk_rst->clk_src_##device, #device, \
225 CLK_DIVIDER(TEGRA_##src##_KHZ, freq), 0xff, src_id)
229 #define clock_configure_source(device, src, freq) \
230 clock_configure_irregular_source(device, src, freq, src)
239 #define clock_configure_i2c_scl_freq(device, src, freq) \
240 _clock_set_div(&clk_rst->clk_src_##device, #device, \
241 DIV_ROUND_UP(TEGRA_##src##_KHZ, (freq) * (0x19 + 1) * 8) - 1, \
257 #define TEGRA_CLK_M_KHZ clock_get_osc_khz()
258 #define TEGRA_PLLX_KHZ CONFIG_PLLX_KHZ
259 #define TEGRA_PLLP_KHZ (408000)
260 #define TEGRA_PLLC_KHZ (600000)
261 #define TEGRA_PLLD_KHZ (925000)
262 #define TEGRA_PLLU_KHZ (960000)
264 #define TEGRA_SCLK_KHZ (300000)
265 #define TEGRA_HCLK_RATIO 1
266 #define TEGRA_HCLK_KHZ (TEGRA_SCLK_KHZ / (1 + TEGRA_HCLK_RATIO))
267 #define TEGRA_PCLK_RATIO 0
268 #define TEGRA_PCLK_KHZ (TEGRA_HCLK_KHZ / (1 + TEGRA_PCLK_RATIO))
static __always_inline void hlt(void)
#define printk(level,...)
#define clrsetbits32(addr, clear, set)
#define BIOS_ERR
BIOS_ERR - System in incomplete state.
int clock_get_pll_input_khz(void)
void clock_cpu0_remove_reset(void)
static void _clock_set_div(u32 *reg, const char *name, u32 div, u32 div_mask, u32 src)
void clock_reset_h(u32 h)
void clock_external_output(int clk_id)
void clock_halt_avp(void)
void sor_clock_stop(void)
void clock_reset_w(u32 w)
int clock_get_osc_khz(void)
void clock_early_uart(void)
void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, u32 ph135, u32 kvco, u32 kcp, u32 stable_time, u32 emc_source, u32 same_freq)
void clock_reset_x(u32 x)
void sor_clock_start(void)
void clock_cpu0_config(void *entry)
u32 clock_display(u32 frequency)
void clock_reset_l(u32 l)
void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x)
void clock_reset_u(u32 u)
void clock_init_arm_generic_timer(void)
void clock_reset_v(u32 v)
#define m(clkreg, src_bits, pmcreg, dst_bits)