coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
xhci.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <amdblocks/gpio.h>
4 #include <amdblocks/smi.h>
5 #include <bootstate.h>
6 #include <device/device.h>
8 #include <soc/pci_devs.h>
9 #include <soc/smi.h>
10 #include <soc/soc_util.h>
11 
12 static const struct sci_source xhci_sci_sources[] = {
13  {
15  .gpe = GEVENT_31,
16  .direction = SMI_SCI_LVL_HIGH,
17  .level = SMI_SCI_EDG
18  },
19  {
20  .scimap = SMITYPE_XHC1_PME,
21  .gpe = GEVENT_31,
22  .direction = SMI_SCI_LVL_HIGH,
23  .level = SMI_SCI_EDG
24  }
25 };
26 
27 enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe)
28 {
29  if (dev->bus->dev->path.type != DEVICE_PATH_PCI)
30  return CB_ERR_ARG;
31 
32  if (dev->bus->dev->path.pci.devfn != PCIE_GPP_A_DEVFN)
33  return CB_ERR_ARG;
34 
35  if (dev->path.type != DEVICE_PATH_PCI)
36  return CB_ERR_ARG;
37 
38  if (dev->path.pci.devfn == XHCI0_DEVFN)
39  *gpe = xhci_sci_sources[0].gpe;
40  else if (dev->path.pci.devfn == XHCI1_DEVFN)
41  *gpe = xhci_sci_sources[1].gpe;
42  else
43  return CB_ERR_ARG;
44 
45  return CB_SUCCESS;
46 }
47 
48 static void configure_xhci_sci(void *unused)
49 {
52  else
54 }
55 
bool soc_is_reduced_io_sku(void)
Definition: soc_util.c:210
@ BS_POST_DEVICE
Definition: bootstate.h:84
@ BS_ON_ENTRY
Definition: bootstate.h:95
#define ARRAY_SIZE(a)
Definition: helpers.h:12
cb_err
coreboot error codes
Definition: cb_err.h:15
@ CB_ERR_ARG
Invalid argument.
Definition: cb_err.h:18
@ CB_SUCCESS
Call completed successfully.
Definition: cb_err.h:16
@ DEVICE_PATH_PCI
Definition: path.h:9
#define XHCI1_DEVFN
Definition: pci_devs.h:88
#define XHCI0_DEVFN
Definition: pci_devs.h:84
#define SMITYPE_XHC1_PME
Definition: smi.h:103
#define SMITYPE_XHC0_PME
Definition: smi.h:102
BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, configure_xhci_sci, NULL)
enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe)
Definition: xhci.c:26
#define GEVENT_31
Definition: gpio_defs.h:297
@ SMI_SCI_EDG
Definition: smi.h:28
@ SMI_SCI_LVL_HIGH
Definition: smi.h:24
void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes)
Definition: smi_util.c:116
#define PCIE_GPP_A_DEVFN
Definition: pci_devs.h:56
static const struct sci_source xhci_sci_sources[]
Definition: xhci.c:12
static void configure_xhci_sci(void *unused)
Definition: xhci.c:48
#define NULL
Definition: stddef.h:19
DEVTREE_CONST struct device * dev
Definition: device.h:78
struct pci_path pci
Definition: path.h:116
enum device_path_type type
Definition: path.h:114
Definition: device.h:107
struct device_path path
Definition: device.h:115
DEVTREE_CONST struct bus * bus
Definition: device.h:108
unsigned int devfn
Definition: path.h:54
Definition: smi.h:37
uint8_t gpe
Definition: smi.h:39
uint8_t scimap
Definition: smi.h:38