coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef _SOC_QUALCOMM_SC7280_GPIO_H_
4 #define _SOC_QUALCOMM_SC7280_GPIO_H_
5 
6 #include <types.h>
7 #include <soc/addressmap.h>
8 #include <soc/gpio_common.h>
9 
10 #define PIN(index, func1, func2, func3, func4) \
11 GPIO##index##_ADDR = TLMM_TILE_BASE + (index * TLMM_GPIO_OFF_DELTA), \
12 GPIO##index##_FUNC_##func1 = 1, \
13 GPIO##index##_FUNC_##func2 = 2, \
14 GPIO##index##_FUNC_##func3 = 3, \
15 GPIO##index##_FUNC_##func4 = 4
16 
17 enum {
18  PIN(0, QUP0_L0, RES_2, RES_3, RES_4),
19  PIN(1, QUP0_L1, RES_2, RES_3, RES_4),
20  PIN(2, QUP0_L2, QUP0_L4, RES_3, RES_4),
21  PIN(3, QUP0_L3, QUP0_L5, RES_3, RES_4),
22  PIN(4, QUP0_L0, RES_2, RES_3, RES_4),
23  PIN(5, QUP0_L1, RES_2, RES_3, RES_4),
24  PIN(6, QUP0_L2, QUP0_L6, RES_3, RES_4),
25  PIN(7, USB_AUDIO_INT_N__SBU_SW_OE, QUP0_L3, RES_3, RES_4),
26  PIN(8, QUP0_L0, RES_2, RES_3, RES_4),
27  PIN(9, QUP0_L1, RES_2, RES_3, RES_4),
28  PIN(10, QUP0_L2, RES_2, RES_3, RES_4),
29  PIN(11, QUP0_L3, RES_2, RES_3, RES_4),
30  PIN(12, QUP0_L0, QSPI_DATA_0, RES_3, RES_4),
31  PIN(13, QUP0_L1, QSPI_DATA_1, RES_3, RES_4),
32  PIN(14, QUP0_L2, QSPI_CLK, RES_3, RES_4),
33  PIN(15, QUP0_L3, QSPI_CS_N_0, RES_3, RES_4),
34  PIN(16, QUP0_L0, QSPI_DATA_2, RES_3, RES_4),
35  PIN(17, QUP0_L1, QSPI_DATA_3, RES_3, RES_4),
36  PIN(18, QUP0_L2, RES_2, RES_3, RES_4),
37  PIN(19, QUP0_L3, QSPI_CS_N_1, RES_3, RES_4),
38  PIN(20, QUP0_L0, CCI_TIMER_0, RES_3, RES_4),
39  PIN(21, QUP0_L1, CCI_TIMER_1, RES_3, RES_4),
40  PIN(22, QUP0_L2, RES_2, RES_3, RES_4),
41  PIN(23, QUP0_L3, RES_2, RES_3, RES_4),
42  PIN(24, QUP0_L0, RES_2, RES_3, RES_4),
43  PIN(25, QUP0_L1, RES_2, RES_3, RES_4),
44  PIN(26, QUP0_L2, RES_2, RES_3, RES_4),
45  PIN(27, QUP0_L3, RES_2, RES_3, RES_4),
46  PIN(28, QUP0_L0, RES_2, RES_3, RES_4),
47  PIN(29, QUP0_L1, RES_2, RES_3, RES_4),
48  PIN(30, QUP0_L2, RES_2, RES_3, RES_4),
49  PIN(31, QUP0_L3, RES_2, RES_3, RES_4),
50  PIN(32, QUP1_L0, RES_2, RES_3, RES_4),
51  PIN(33, QUP1_L1, RES_2, RES_3, RES_4),
52  PIN(34, QUP1_L2, RES_2, RES_3, RES_4),
53  PIN(35, QUP1_L3, RES_2, RES_3, RES_4),
54  PIN(36, QUP1_L0, RES_2, RES_3, RES_4),
55  PIN(37, QUP1_L1, RES_2, RES_3, RES_4),
56  PIN(38, QUP1_L2, QUP1_L6, RES_3, RES_4),
57  PIN(39, QUP1_L3, RES_2, RES_3, RES_4),
58  PIN(40, QUP1_L0, RES_2, RES_3, RES_4),
59  PIN(41, QUP1_L1, RES_2, RES_3, RES_4),
60  PIN(42, QUP1_L2, RES_2, RES_3, RES_4),
61  PIN(43, QUP1_L3, RES_2, RES_3, RES_4),
62  PIN(44, QUP1_L0, RES_2, RES_3, RES_4),
63  PIN(45, QUP1_L1, RES_2, RES_3, RES_4),
64  PIN(46, QUP1_L2, RES_2, RES_3, RES_4),
65  PIN(47, QUP1_L3, DP_HOT_PLUG_DETECT, RES_3, RES_4),
66  PIN(48, QUP1_L0, RES_2, RES_3, RES_4),
67  PIN(49, QUP1_L1, RES_2, RES_3, RES_4),
68  PIN(50, QUP1_L2, QUP1_L6, RES_3, RES_4),
69  PIN(51, QUP1_L3, RES_2, RES_3, RES_4),
70  PIN(52, QUP1_L0, RES_2, RES_3, RES_4),
71  PIN(53, QUP1_L1, RES_2, RES_3, RES_4),
72  PIN(54, QUP1_L2, QUP1_L5, RES_3, RES_4),
73  PIN(55, QUP1_L3, QUP1_L4, RES_3, RES_4),
74  PIN(56, QUP1_L0, RES_2, RES_3, RES_4),
75  PIN(57, QUP1_L1, RES_2, RES_3, RES_4),
76  PIN(58, QUP1_L2, RES_2, RES_3, RES_4),
77  PIN(59, QUP1_L3, RES_2, RES_3, RES_4),
78  PIN(60, QUP1_L0, EDP_HOT_PLUG_DETECT, RES_3, RES_4),
79  PIN(61, QUP1_L1, SD_WRITE_PROTECT, RES_3, RES_4),
80  PIN(62, QUP1_L2, QUP1_L4, RES_3, RES_4),
81  PIN(63, QUP1_L3, QUP1_L5, RES_3, RES_4),
82  PIN(64, CAM_MCLK0, RES_2, RES_3, RES_4),
83  PIN(65, CAM_MCLK1, RES_2, RES_3, RES_4),
84  PIN(66, CAM_MCLK2, RES_2, RES_3, RES_4),
85  PIN(67, CAM_MCLK3, RES_2, RES_3, RES_4),
86  PIN(68, CAM_MCLK4, RES_2, RES_3, RES_4),
87  PIN(69, CCI_I2C_SDA0, RES_2, RES_3, RES_4),
88  PIN(70, CCI_I2C_SCL0, RES_2, RES_3, RES_4),
89  PIN(71, CCI_I2C_SDA1, RES_2, RES_3, RES_4),
90  PIN(72, CCI_I2C_SCL1, RES_2, RES_3, RES_4),
91  PIN(73, CCI_I2C_SDA2, RES_2, RES_3, RES_4),
92  PIN(74, CCI_I2C_SCL2, RES_2, RES_3, RES_4),
93  PIN(75, CCI_I2C_SDA3, RES_2, RES_3, RES_4),
94  PIN(76, CCI_I2C_SCL3, GCC_GP1_CLK_MIRB, RES_3, RES_4),
95  PIN(77, CCI_TIMER2, GCC_GP2_CLK_MIRB, RES_3, RES_4),
96  PIN(78, CCI_TIMER3, CCI_ASYNC_IN1, GCC_GP3_CLK_MIRB, RES_4),
97  PIN(79, CCI_TIMER4, CCI_ASYNC_IN2, RES_3, RES_4),
98  PIN(80, RES_1, RES_2, RES_3, RES_4),
99  PIN(81, RES_1, RES_2, RES_3, RES_4),
100  PIN(82, RES_1, RES_2, RES_3, RES_4),
101  PIN(83, RES_1, RES_2, RES_3, RES_4),
102  PIN(84, USB2PHY_AC_EN0, RES_2, RES_3, RES_4),
103  PIN(85, USB2PHY_AC_EN1, RES_2, RES_3, RES_4),
104  PIN(86, RES_1, RES_2, RES_3, RES_4),
105  PIN(87, RES_1, RES_2, RES_3, RES_4),
106  PIN(88, RES_1, RES_2, RES_3, RES_4),
107  PIN(89, RES_1, RES_2, RES_3, RES_4),
108  PIN(90, RES_1, RES_2, RES_3, RES_4),
109  PIN(91, RES_1, RES_2, RES_3, RES_4),
110  PIN(92, RES_1, RES_2, RES_3, RES_4),
111  PIN(93, CAM_MCLK5, CCI_ASYNC_IN0, RES_3, RES_4),
112  PIN(94, LPASS_SLIMBUS_CLK, RES_2, RES_3, RES_4),
113  PIN(95, LPASS_SLIMBUS_DATA0, RES_2, RES_3, RES_4),
114  PIN(96, PRI_MI2S_MCLK, RES_2, RES_3, RES_4),
115  PIN(97, MI2S0_SCK, RES_2, RES_3, RES_4),
116  PIN(98, MI2S0_DATA0, RES_2, RES_3, RES_4),
117  PIN(99, MI2S0_DATA1, RES_2, RES_3, RES_4),
118  PIN(100, MI2S0_WS, RES_2, RES_3, RES_4),
119  PIN(101, MI2S2_SCK, RES_2, RES_3, RES_4),
120  PIN(102, MI2S2_DATA0, RES_2, RES_3, RES_4),
121  PIN(103, MI2S2_WS, RES_2, RES_3, RES_4),
122  PIN(104, MI2S2_DATA1, RES_2, RES_3, RES_4),
123  PIN(105, SEC_MI2S_MCLK, MI2S1_DATA1, RES_3, GCC_GP1_CLK_MIRA),
124  PIN(106, MI2S1_SCK, GCC_GP2_CLK_MIRA, RES_3, RES_4),
125  PIN(107, MI2S1_DATA0, GCC_GP3_CLK_MIRA, RES_3, RES_4),
126  PIN(108, MI2S1_WS, RES_2, RES_3, RES_4),
127  PIN(109, RES_1, RES_2, RES_3, RES_4),
128  PIN(110, RES_1, RES_2, RES_3, RES_4),
129  PIN(111, RES_1, RES_2, RES_3, RES_4),
130  PIN(112, RES_1, RES_2, RES_3, RES_4),
131  PIN(113, RES_1, RES_2, RES_3, RES_4),
132  PIN(114, RES_1, RES_2, RES_3, RES_4),
133  PIN(115, RES_1, RES_2, RES_3, RES_4),
134  PIN(116, RES_1, RES_2, RES_3, RES_4),
135  PIN(117, RES_1, RES_2, RES_3, RES_4),
136  PIN(118, RES_1, RES_2, RES_3, RES_4),
137  PIN(119, RES_1, RES_2, RES_3, RES_4),
138  PIN(120, RES_1, RES_2, RES_3, RES_4),
139  PIN(121, RES_1, RES_2, RES_3, RES_4),
140  PIN(122, RES_1, RES_2, RES_3, RES_4),
141  PIN(123, RES_1, RES_2, RES_3, RES_4),
142  PIN(124, RES_1, RES_2, RES_3, RES_4),
143  PIN(125, RES_1, RES_2, RES_3, RES_4),
144  PIN(126, RES_1, RES_2, RES_3, RES_4),
145  PIN(127, RES_1, RES_2, RES_3, RES_4),
146  PIN(128, RES_1, RES_2, RES_3, RES_4),
147  PIN(129, RES_1, RES_2, RES_3, RES_4),
148  PIN(130, RES_1, RES_2, RES_3, RES_4),
149  PIN(131, RES_1, RES_2, RES_3, RES_4),
150  PIN(132, RES_1, RES_2, RES_3, RES_4),
151  PIN(133, RES_1, RES_2, RES_3, RES_4),
152  PIN(134, RES_1, RES_2, RES_3, RES_4),
153  PIN(135, RES_1, RES_2, RES_3, RES_4),
154  PIN(136, RES_1, RES_2, RES_3, RES_4),
155  PIN(137, RES_1, RES_2, RES_3, RES_4),
156  PIN(138, RES_1, RES_2, RES_3, RES_4),
157  PIN(139, RES_1, RES_2, RES_3, RES_4),
158  PIN(140, USB_PHY_PS, RES_2, RES_3, RES_4),
159  PIN(141, RES_1, RES_2, RES_3, RES_4),
160  PIN(142, RES_1, RES_2, RES_3, RES_4),
161  PIN(143, RES_1, RES_2, RES_3, RES_4),
162  PIN(144, RES_1, RES_2, RES_3, RES_4),
163  PIN(145, RES_1, RES_2, RES_3, RES_4),
164  PIN(146, RES_1, RES_2, RES_3, RES_4),
165  PIN(147, RES_1, RES_2, RES_3, RES_4),
166  PIN(148, RES_1, RES_2, RES_3, RES_4),
167  PIN(149, RES_1, RES_2, RES_3, RES_4),
168  PIN(150, RES_1, RES_2, RES_3, RES_4),
169  PIN(151, RES_1, RES_2, RES_3, RES_4),
170  PIN(152, RES_1, RES_2, RES_3, RES_4),
171  PIN(153, RES_1, RES_2, RES_3, RES_4),
172  PIN(154, RES_1, RES_2, RES_3, RES_4),
173  PIN(155, RES_1, RES_2, RES_3, RES_4),
174  PIN(156, RES_1, RES_2, RES_3, RES_4),
175  PIN(157, RES_1, RES_2, RES_3, RES_4),
176  PIN(158, RES_1, RES_2, RES_3, RES_4),
177  PIN(159, RES_1, RES_2, RES_3, RES_4),
178  PIN(160, RES_1, RES_2, RES_3, RES_4),
179  PIN(161, RES_1, RES_2, RES_3, RES_4),
180  PIN(162, RES_1, RES_2, RES_3, RES_4),
181  PIN(163, RES_1, RES_2, RES_3, RES_4),
182  PIN(164, RES_1, RES_2, RES_3, RES_4),
183  PIN(165, RES_1, RES_2, RES_3, RES_4),
184  PIN(166, RES_1, RES_2, RES_3, RES_4),
185  PIN(167, RES_1, RES_2, RES_3, RES_4),
186  PIN(168, RES_1, RES_2, RES_3, RES_4),
187  PIN(169, RES_1, RES_2, RES_3, RES_4),
188  PIN(170, RES_1, RES_2, RES_3, RES_4),
189  PIN(171, RES_1, RES_2, RES_3, RES_4),
190  PIN(172, RES_1, RES_2, RES_3, RES_4),
191  PIN(173, RES_1, RES_2, RES_3, RES_4),
192  PIN(174, RES_1, RES_2, RES_3, RES_4),
193 };
194 
195 #endif /* _SOC_QUALCOMM_SC7280_GPIO_H_ */
QSPI_DATA_1
#define QSPI_DATA_1
Definition: addressmap.h:52
QSPI_DATA_0
#define QSPI_DATA_0
Definition: addressmap.h:51
QSPI_CLK
#define QSPI_CLK
Definition: addressmap.h:50
PIN
#define PIN(index, func1, func2, func3, func4)
Definition: gpio.h:10