coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
ec.c
Go to the documentation of this file.
1
/* SPDX-License-Identifier: GPL-2.0-only */
2
3
#include <
acpi/acpi.h
>
4
#include <
console/console.h
>
5
#include <
ec/google/chromeec/ec.h
>
6
#include <
amdblocks/lpc.h
>
7
#include <soc/southbridge.h>
8
#include <variant/ec.h>
9
10
static
void
ramstage_ec_init
(
void
)
11
{
12
const
struct
google_chromeec_event_info
info
= {
13
.log_events =
MAINBOARD_EC_LOG_EVENTS
,
14
.sci_events =
MAINBOARD_EC_SCI_EVENTS
,
15
.s3_wake_events =
MAINBOARD_EC_S3_WAKE_EVENTS
,
16
.s5_wake_events =
MAINBOARD_EC_S5_WAKE_EVENTS
,
17
};
18
19
printk
(
BIOS_DEBUG
,
"mainboard: EC init\n"
);
20
21
google_chromeec_events_init
(&
info
,
acpi_is_wakeup_s3
());
22
}
23
24
static
void
early_ec_init
(
void
)
25
{
26
uint16_t
ec_ioport_base;
27
size_t
ec_ioport_size;
28
int
status;
29
30
/*
31
* Set up LPC decoding for the ChromeEC I/O port ranges:
32
* - Ports 62/66, 60/64, and 200->208
33
* -- set by hudson_lpc_decode() in pre
34
* - ChromeEC specific communication I/O ports.
35
*/
36
google_chromeec_ioport_range
(&ec_ioport_base, &ec_ioport_size);
37
printk
(
BIOS_DEBUG
,
38
"LPC Setup google_chromeec_ioport_range: %04x, %08zx\n"
,
39
ec_ioport_base, ec_ioport_size);
40
status =
lpc_set_wideio_range
(ec_ioport_base, ec_ioport_size);
41
if
(status ==
WIDEIO_RANGE_ERROR
)
42
printk
(
BIOS_ERR
,
"Failed to assign a range\n"
);
43
else
44
printk
(
BIOS_DEBUG
,
"Range assigned to wide IO %d\n"
, status);
45
}
46
47
void
mainboard_ec_init
(
void
)
48
{
49
if
(
ENV_RAMSTAGE
)
50
ramstage_ec_init
();
51
else
52
early_ec_init
();
53
}
acpi_is_wakeup_s3
static int acpi_is_wakeup_s3(void)
Definition:
acpi.h:9
printk
#define printk(level,...)
Definition:
stdlib.h:16
console.h
info
static struct smmstore_params_info info
Definition:
ramstage.c:12
google_chromeec_events_init
void google_chromeec_events_init(const struct google_chromeec_event_info *info, bool is_s3_wakeup)
Definition:
ec.c:410
ec.h
google_chromeec_ioport_range
void google_chromeec_ioport_range(uint16_t *base, size_t *size)
Definition:
ec_lpc.c:364
acpi.h
BIOS_DEBUG
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
Definition:
loglevel.h:128
BIOS_ERR
#define BIOS_ERR
BIOS_ERR - System in incomplete state.
Definition:
loglevel.h:72
mainboard_ec_init
void mainboard_ec_init(void)
Definition:
ec.c:8
MAINBOARD_EC_S5_WAKE_EVENTS
#define MAINBOARD_EC_S5_WAKE_EVENTS
Definition:
ec.h:32
MAINBOARD_EC_SCI_EVENTS
#define MAINBOARD_EC_SCI_EVENTS
Definition:
ec.h:12
MAINBOARD_EC_LOG_EVENTS
#define MAINBOARD_EC_LOG_EVENTS
Definition:
ec.h:42
MAINBOARD_EC_S3_WAKE_EVENTS
#define MAINBOARD_EC_S3_WAKE_EVENTS
Definition:
ec.h:37
ramstage_ec_init
static void ramstage_ec_init(void)
Definition:
ec.c:10
early_ec_init
static void early_ec_init(void)
Definition:
ec.c:24
ENV_RAMSTAGE
#define ENV_RAMSTAGE
Definition:
rules.h:150
lpc.h
WIDEIO_RANGE_ERROR
#define WIDEIO_RANGE_ERROR
Definition:
lpc.h:70
lpc_set_wideio_range
int lpc_set_wideio_range(uint16_t start, uint16_t size)
Program a LPC wide IO to support an IO range.
Definition:
lpc_util.c:109
uint16_t
unsigned short uint16_t
Definition:
stdint.h:11
google_chromeec_event_info
Definition:
ec.h:194
src
mainboard
google
kahlee
ec.c
Generated by
1.9.1