coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.c
Go to the documentation of this file.
1
/* SPDX-License-Identifier: GPL-2.0-or-later */
2
3
#include <baseboard/gpio.h>
4
#include <baseboard/variants.h>
5
#include <
commonlib/helpers.h
>
6
7
/* Pad configuration in ramstage */
8
static
const
struct
pad_config
override_gpio_table
[] = {
9
/* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */
10
PAD_CFG_GPO
(
GPP_A7
, 1, DEEP),
11
/* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */
12
PAD_CFG_GPO
(
GPP_A8
, 0, DEEP),
13
/* A10 : I2S2_RXD ==> EN_SPKR_PA */
14
PAD_CFG_GPO
(
GPP_A10
, 1, DEEP),
15
/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
16
PAD_CFG_GPO
(
GPP_A13
, 1, DEEP),
17
/* A16 : USB_OC3# ==> USB_C0_OC_ODL */
18
PAD_CFG_NF
(
GPP_A16
,
NONE
, DEEP, NF1),
19
/* A18 : DDSP_HPDB ==> HDMI_HPD */
20
PAD_CFG_NF
(
GPP_A18
,
NONE
, DEEP, NF1),
21
/* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */
22
PAD_CFG_NF
(
GPP_A19
,
NONE
, DEEP, NF1),
23
/* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */
24
PAD_CFG_NF
(
GPP_A20
,
NONE
, DEEP, NF1),
25
/* A21 : DDPC_CTRCLK ==> EN_FP_PWR */
26
PAD_CFG_GPO
(
GPP_A21
, 1, DEEP),
27
/* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */
28
PAD_CFG_GPO
(
GPP_A22
, 1, DEEP),
29
/* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */
30
PAD_CFG_NF
(
GPP_A23
,
NONE
, DEEP, NF1),
31
32
/* B3 : CPU_GP2 ==> PEN_DET_ODL */
33
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_B3
,
NONE
, PLTRST),
34
/* B5 : ISH_I2C0_CVF_SDA */
35
PAD_CFG_NF
(
GPP_B5
,
NONE
, DEEP, NF1),
36
/* B6 : ISH_I2C0_CVF_SCL */
37
PAD_CFG_NF
(
GPP_B6
,
NONE
, DEEP, NF1),
38
/* B7 : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */
39
PAD_CFG_NF
(
GPP_B7
,
NONE
, DEEP, NF1),
40
/* B8 : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */
41
PAD_CFG_NF
(
GPP_B8
,
NONE
, DEEP, NF1),
42
/* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */
43
PAD_CFG_NF
(
GPP_B9
,
NONE
, DEEP, NF1),
44
/* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */
45
PAD_CFG_NF
(
GPP_B10
,
NONE
, DEEP, NF1),
46
/* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */
47
PAD_CFG_NF
(
GPP_B19
,
NONE
, DEEP, NF1),
48
/* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */
49
PAD_CFG_NF
(
GPP_B20
,
NONE
, DEEP, NF1),
50
/* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */
51
PAD_CFG_NF
(
GPP_B21
,
NONE
, DEEP, NF1),
52
53
/* C0 : SMBCLK ==> EN_PP3300_WLAN */
54
PAD_CFG_GPO
(
GPP_C0
, 1, DEEP),
55
/* C7 : SML1DATA ==> EN_USI_CHARGE */
56
PAD_CFG_GPO
(
GPP_C7
, 1, DEEP),
57
/* C10 : UART0_RTS# ==> USI_RST_L */
58
PAD_CFG_GPO
(
GPP_C10
, 0, DEEP),
59
/* C13 : UART1_TXD ==> EN_PP5000_TRACKPAD */
60
PAD_CFG_GPO
(
GPP_C13
, 1, DEEP),
61
/* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */
62
PAD_CFG_NF
(
GPP_C16
,
NONE
, DEEP, NF1),
63
/* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */
64
PAD_CFG_NF
(
GPP_C17
,
NONE
, DEEP, NF1),
65
/* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */
66
PAD_CFG_NF
(
GPP_C18
,
NONE
, DEEP, NF1),
67
/* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */
68
PAD_CFG_NF
(
GPP_C19
,
NONE
, DEEP, NF1),
69
/* C20 : UART2_RXD ==> FPMCU_INT_L */
70
/* APIC interrupt conflict, so used GPI_INT; see b/147500717 */
71
PAD_CFG_GPI_INT
(
GPP_C20
,
NONE
, PLTRST, LEVEL),
72
/* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
73
PAD_CFG_GPO
(
GPP_C22
, 0, DEEP),
74
/* C23 : UART2_CTS# ==> FPMCU_RST_ODL */
75
PAD_CFG_GPO
(
GPP_C23
, 1, DEEP),
76
77
/* D1 : ISH_GP1 ==> ISH_ACCEL_INT_L */
78
PAD_CFG_GPI
(
GPP_D1
,
NONE
, DEEP),
79
/* D2 : ISH_GP2 ==> ISH_LID_OPEN */
80
PAD_CFG_GPI
(
GPP_D2
,
NONE
, DEEP),
81
/* D3 : ISH_GP3 ==> ISH_ALS_RGB_INT_L */
82
PAD_CFG_GPI
(
GPP_D3
,
NONE
, DEEP),
83
/* D4 : IMGCLKOUT0 ==> FCAM_RST_L */
84
PAD_CFG_GPO
(
GPP_D4
, 0, PLTRST),
85
/* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */
86
PAD_CFG_NF
(
GPP_D6
,
NONE
, DEEP, NF1),
87
/* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
88
PAD_CFG_NF
(
GPP_D8
,
NONE
, DEEP, NF1),
89
/* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */
90
PAD_CFG_NF
(
GPP_D13
,
NONE
, DEEP, NF1),
91
/* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */
92
PAD_CFG_NF
(
GPP_D14
,
NONE
, DEEP, NF1),
93
/* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
94
PAD_NC
(
GPP_D16
, UP_20K),
95
/* D17 : ISH_GP4 ==> EN_FCAM_PWR */
96
PAD_CFG_GPO
(
GPP_D17
, 0, DEEP),
97
/* D18 : ISH_GP5 ==> FCAM_SNRPWR_EN */
98
PAD_CFG_GPO
(
GPP_D18
, 0, DEEP),
99
100
/* E1 : SPI1_IO2 ==> PEN_DET_ODL */
101
PAD_CFG_GPI_SCI
(
GPP_E1
,
NONE
, DEEP, EDGE_SINGLE,
NONE
),
102
/* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */
103
PAD_CFG_GPI
(
GPP_E2
,
NONE
, DEEP),
104
/* E3 : CPU_GP0 ==> USI_REPORT_EN */
105
PAD_CFG_GPO
(
GPP_E3
, 0, DEEP),
106
/* E7 : CPU_GP1 ==> USI_INT */
107
PAD_CFG_GPI_APIC
(
GPP_E7
,
NONE
, PLTRST, LEVEL,
NONE
),
108
/* E8 : SPI1_CS1# ==> SLP_S0IX */
109
PAD_CFG_GPO
(
GPP_E8
, 0, DEEP),
110
/* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */
111
PAD_CFG_GPI
(
GPP_E11
,
NONE
, DEEP),
112
/* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */
113
PAD_CFG_GPI_IRQ_WAKE(
GPP_E15
,
NONE
, DEEP, LEVEL, INVERT),
114
/* E16 : ISH_GP7 ==> WWAN_SIM1_DET_OD */
115
PAD_CFG_GPI
(
GPP_E16
,
NONE
, DEEP),
116
/* E17 : THC0_SPI1_INT# ==> WWAN_PERST_L */
117
PAD_CFG_GPO
(
GPP_E17
, 1, DEEP),
118
119
/* F6 : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */
120
PAD_CFG_NF
(
GPP_F6
,
NONE
, DEEP, NF1),
121
/* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */
122
PAD_CFG_GPI_INT
(
GPP_F8
,
NONE
, PLTRST, EDGE_BOTH),
123
/* F12 : GSXDOUT ==> WWAN_RST_ODL */
124
PAD_CFG_GPI
(
GPP_F12
,
NONE
, DEEP),
125
/* F13 : GSXDOUT ==> WiFi_DISABLE_L */
126
PAD_CFG_GPO
(
GPP_F13
, 1, DEEP),
127
/* F14 : GSXDIN ==> SAR0_INT_L */
128
PAD_CFG_GPI_APIC
(
GPP_F14
,
NONE
, PLTRST, LEVEL,
NONE
),
129
/* F15 : GSXSRESET# ==> RCAM_RST_L */
130
PAD_CFG_GPO
(
GPP_F15
, 1, DEEP),
131
/* F16 : GSXCLK ==> WWAN_DPR_SAR_ODL */
132
PAD_CFG_GPO
(
GPP_F16
, 1, DEEP),
133
/* F17 : WWAN_RF_DISABLE_ODL */
134
PAD_CFG_GPO
(
GPP_F17
, 1, DEEP),
135
/* F18 : THC1_SPI2_INT# ==> WWAN_PCIE_WAKE_ODL */
136
PAD_CFG_GPI_SCI_LOW
(
GPP_F18
,
NONE
, DEEP, EDGE_SINGLE),
137
/* F19 : SRCCLKREQ6# ==> WLAN_INT_L */
138
PAD_CFG_GPI_SCI_LOW
(
GPP_F19
,
NONE
, DEEP, EDGE_SINGLE),
139
140
/* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */
141
PAD_CFG_GPO
(
GPP_H3
, 1, DEEP),
142
/* H6 : I2C3_SDA ==> PCH_I2C3_CAM_SDA */
143
PAD_CFG_NF
(
GPP_H6
,
NONE
, DEEP, NF1),
144
/* H7 : I2C3_SCL ==> PCH_I2C3_CAM_SCL */
145
PAD_CFG_NF
(
GPP_H7
,
NONE
, DEEP, NF1),
146
/* H8 : I2C4_SDA ==> WWAN_WLAN_COEX1 */
147
PAD_CFG_NF
(
GPP_H8
,
NONE
, DEEP, NF2),
148
/* H9 : I2C4_SCL ==> WWAN_WLAN_COEX2 */
149
PAD_CFG_NF
(
GPP_H9
,
NONE
, DEEP, NF2),
150
/* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */
151
PAD_CFG_GPO
(
GPP_H11
, 1, DEEP),
152
/* H12 : M2_SKT2_CFG0 ==> WWAN_CONFIG0 */
153
PAD_CFG_GPI
(
GPP_H12
,
NONE
, DEEP),
154
/* H13 : M2_SKT2_CFG1 # ==> WWAN_CONFIG1 */
155
PAD_CFG_GPI
(
GPP_H13
,
NONE
, DEEP),
156
/* H14 : M2_SKT2_CFG2 # ==> RCAM_SNRPWR_EN */
157
PAD_CFG_GPO
(
GPP_H14
, 0, DEEP),
158
/* H15 : M2_SKT2_CFG3 # ==> WWAN_CONFIG3 */
159
PAD_CFG_GPI
(
GPP_H15
,
NONE
, DEEP),
160
/* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */
161
PAD_CFG_NF
(
GPP_H16
,
NONE
, DEEP, NF1),
162
/* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */
163
PAD_CFG_NF
(
GPP_H17
,
NONE
, DEEP, NF1),
164
/* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */
165
PAD_CFG_GPI
(
GPP_H19
,
NONE
, DEEP),
166
/* H20 : IMGCLKOUT1 ==> EN_MIPI_RCAM_PWR */
167
PAD_CFG_GPO
(
GPP_H20
, 0, DEEP),
168
/* H21 : IMGCLKOUT2 ==> CAM_MCLK1 */
169
PAD_CFG_NF
(
GPP_H21
,
NONE
, DEEP, NF1),
170
/* H22 : IMGCLKOUT3 ==> CAM_MCLK0 */
171
PAD_CFG_NF
(
GPP_H22
,
NONE
, DEEP, NF1),
172
173
/* R0 : HDA_BCLK ==> I2S0_HP_SCLK */
174
PAD_CFG_NF
(
GPP_R0
,
NONE
, DEEP, NF2),
175
/* R1 : HDA_SYNC ==> I2S0_HP_SFRM */
176
PAD_CFG_NF
(
GPP_R1
,
NONE
, DEEP, NF2),
177
/* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */
178
PAD_CFG_NF
(
GPP_R2
, DN_20K, DEEP, NF2),
179
/* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */
180
PAD_CFG_NF
(
GPP_R3
,
NONE
, DEEP, NF2),
181
/* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */
182
PAD_CFG_NF
(
GPP_R5
,
NONE
, DEEP, NF2),
183
/* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */
184
PAD_CFG_NF
(
GPP_R6
,
NONE
, DEEP, NF2),
185
/* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */
186
PAD_CFG_NF
(
GPP_R7
,
NONE
, DEEP, NF2),
187
188
/* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */
189
PAD_CFG_NF
(
GPP_S0
,
NONE
, DEEP, NF1),
190
/* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */
191
PAD_CFG_NF
(
GPP_S1
,
NONE
, DEEP, NF1),
192
/* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */
193
PAD_CFG_NF
(
GPP_S2
,
NONE
, DEEP, NF1),
194
/* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */
195
PAD_CFG_NF
(
GPP_S3
,
NONE
, DEEP, NF1),
196
/* S4 : SNDW2_CLK ==> DMIC_CLK1 */
197
PAD_CFG_NF
(
GPP_S4
,
NONE
, DEEP, NF2),
198
/* S5 : SNDW2_DATA ==> DMIC_DATA1 */
199
PAD_CFG_NF
(
GPP_S5
,
NONE
, DEEP, NF2),
200
/* S6 : SNDW3_CLK ==> DMIC_CLK0 */
201
PAD_CFG_NF
(
GPP_S6
,
NONE
, DEEP, NF2),
202
/* S7 : SNDW3_DATA ==> DMIC_DATA0 */
203
PAD_CFG_NF
(
GPP_S7
,
NONE
, DEEP, NF2),
204
205
/* GPD9: SLP_WLAN# ==> SLP_WLAN_L */
206
PAD_CFG_NF
(
GPD9
,
NONE
, DEEP, NF1),
207
};
208
209
/* Early pad configuration in bootblock */
210
static
const
struct
pad_config
early_gpio_table
[] = {
211
/* C8 : UART0 RX */
212
PAD_CFG_NF
(
GPP_C8
,
NONE
, DEEP, NF1),
213
/* C9 : UART0 TX */
214
PAD_CFG_NF
(
GPP_C9
,
NONE
, DEEP, NF1),
215
216
/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
217
PAD_CFG_NF
(
GPP_A12
,
NONE
, DEEP, NF1),
218
/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
219
/* assert reset on reboot */
220
PAD_CFG_GPO
(
GPP_A13
, 0, DEEP),
221
/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
222
PAD_CFG_GPI
(
GPP_A17
,
NONE
, DEEP),
223
224
/* B11 : PMCALERT# ==> PCH_WP_OD */
225
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_B11
,
NONE
, DEEP),
226
/* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
227
PAD_CFG_NF
(
GPP_B15
,
NONE
, DEEP, NF1),
228
/* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */
229
PAD_CFG_NF
(
GPP_B16
,
NONE
, DEEP, NF1),
230
/* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */
231
PAD_CFG_NF
(
GPP_B17
,
NONE
, DEEP, NF1),
232
/* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
233
PAD_CFG_NF
(
GPP_B18
,
NONE
, DEEP, NF1),
234
235
/* C0 : SMBCLK ==> EN_PP3300_WLAN */
236
PAD_CFG_GPO
(
GPP_C0
, 1, DEEP),
237
/* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
238
PAD_CFG_GPI_APIC
(
GPP_C21
,
NONE
, PLTRST, LEVEL, INVERT),
239
/* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
240
PAD_CFG_GPO
(
GPP_C22
, 0, DEEP),
241
242
/* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
243
PAD_NC
(
GPP_D16
, UP_20K),
244
245
/* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */
246
PAD_CFG_GPO
(
GPP_F11
, 1, DEEP),
247
/* F12 : GSXDOUT ==> WWAN_RST_ODL
248
To meet timing constrains - drive reset low.
249
Deasserted in ramstage. */
250
PAD_CFG_GPO
(
GPP_F12
, 0, DEEP),
251
252
/* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */
253
PAD_CFG_GPO
(
GPP_H11
, 1, DEEP),
254
};
255
256
const
struct
pad_config
*
variant_override_gpio_table
(
size_t
*num)
257
{
258
*num =
ARRAY_SIZE
(
override_gpio_table
);
259
return
override_gpio_table
;
260
}
261
262
const
struct
pad_config
*
variant_early_gpio_table
(
size_t
*num)
263
{
264
*num =
ARRAY_SIZE
(
early_gpio_table
);
265
return
early_gpio_table
;
266
}
GPP_H22
#define GPP_H22
Definition:
gpio_soc_defs.h:238
GPP_H20
#define GPP_H20
Definition:
gpio_soc_defs.h:236
GPP_B6
#define GPP_B6
Definition:
gpio_soc_defs.h:59
GPP_H19
#define GPP_H19
Definition:
gpio_soc_defs.h:235
GPP_D1
#define GPP_D1
Definition:
gpio_soc_defs.h:253
GPD9
#define GPD9
Definition:
gpio_soc_defs.h:390
GPP_D8
#define GPP_D8
Definition:
gpio_soc_defs.h:260
GPP_D17
#define GPP_D17
Definition:
gpio_soc_defs.h:269
GPP_E3
#define GPP_E3
Definition:
gpio_soc_defs.h:631
GPP_A18
#define GPP_A18
Definition:
gpio_soc_defs.h:137
GPP_F12
#define GPP_F12
Definition:
gpio_soc_defs.h:585
GPP_F16
#define GPP_F16
Definition:
gpio_soc_defs.h:589
GPP_S4
#define GPP_S4
Definition:
gpio_soc_defs.h:164
GPP_H15
#define GPP_H15
Definition:
gpio_soc_defs.h:231
GPP_H16
#define GPP_H16
Definition:
gpio_soc_defs.h:232
GPP_R7
#define GPP_R7
Definition:
gpio_soc_defs.h:676
GPP_F6
#define GPP_F6
Definition:
gpio_soc_defs.h:579
GPP_D14
#define GPP_D14
Definition:
gpio_soc_defs.h:266
GPP_S0
#define GPP_S0
Definition:
gpio_soc_defs.h:160
GPP_H11
#define GPP_H11
Definition:
gpio_soc_defs.h:227
GPP_H17
#define GPP_H17
Definition:
gpio_soc_defs.h:233
GPP_S5
#define GPP_S5
Definition:
gpio_soc_defs.h:165
GPP_B16
#define GPP_B16
Definition:
gpio_soc_defs.h:69
GPP_R3
#define GPP_R3
Definition:
gpio_soc_defs.h:672
GPP_D6
#define GPP_D6
Definition:
gpio_soc_defs.h:258
GPP_A19
#define GPP_A19
Definition:
gpio_soc_defs.h:138
GPP_D2
#define GPP_D2
Definition:
gpio_soc_defs.h:254
GPP_H12
#define GPP_H12
Definition:
gpio_soc_defs.h:228
GPP_H6
#define GPP_H6
Definition:
gpio_soc_defs.h:222
GPP_C9
#define GPP_C9
Definition:
gpio_soc_defs.h:546
GPP_C22
#define GPP_C22
Definition:
gpio_soc_defs.h:559
GPP_R6
#define GPP_R6
Definition:
gpio_soc_defs.h:675
GPP_H9
#define GPP_H9
Definition:
gpio_soc_defs.h:225
GPP_R0
#define GPP_R0
Definition:
gpio_soc_defs.h:669
GPP_B15
#define GPP_B15
Definition:
gpio_soc_defs.h:68
GPP_H21
#define GPP_H21
Definition:
gpio_soc_defs.h:237
GPP_C23
#define GPP_C23
Definition:
gpio_soc_defs.h:560
GPP_H13
#define GPP_H13
Definition:
gpio_soc_defs.h:229
GPP_C8
#define GPP_C8
Definition:
gpio_soc_defs.h:545
GPP_S7
#define GPP_S7
Definition:
gpio_soc_defs.h:167
GPP_H7
#define GPP_H7
Definition:
gpio_soc_defs.h:223
GPP_H14
#define GPP_H14
Definition:
gpio_soc_defs.h:230
GPP_A23
#define GPP_A23
Definition:
gpio_soc_defs.h:142
GPP_C18
#define GPP_C18
Definition:
gpio_soc_defs.h:555
GPP_S3
#define GPP_S3
Definition:
gpio_soc_defs.h:163
GPP_C13
#define GPP_C13
Definition:
gpio_soc_defs.h:550
GPP_C17
#define GPP_C17
Definition:
gpio_soc_defs.h:554
GPP_E8
#define GPP_E8
Definition:
gpio_soc_defs.h:636
GPP_A7
#define GPP_A7
Definition:
gpio_soc_defs.h:126
GPP_B8
#define GPP_B8
Definition:
gpio_soc_defs.h:61
GPP_S1
#define GPP_S1
Definition:
gpio_soc_defs.h:161
GPP_C20
#define GPP_C20
Definition:
gpio_soc_defs.h:557
GPP_B20
#define GPP_B20
Definition:
gpio_soc_defs.h:73
GPP_A20
#define GPP_A20
Definition:
gpio_soc_defs.h:139
GPP_A16
#define GPP_A16
Definition:
gpio_soc_defs.h:135
GPP_F17
#define GPP_F17
Definition:
gpio_soc_defs.h:590
GPP_A12
#define GPP_A12
Definition:
gpio_soc_defs.h:131
GPP_F15
#define GPP_F15
Definition:
gpio_soc_defs.h:588
GPP_D4
#define GPP_D4
Definition:
gpio_soc_defs.h:256
GPP_C10
#define GPP_C10
Definition:
gpio_soc_defs.h:547
GPP_E7
#define GPP_E7
Definition:
gpio_soc_defs.h:635
GPP_C16
#define GPP_C16
Definition:
gpio_soc_defs.h:553
GPP_F13
#define GPP_F13
Definition:
gpio_soc_defs.h:586
GPP_D18
#define GPP_D18
Definition:
gpio_soc_defs.h:270
GPP_S6
#define GPP_S6
Definition:
gpio_soc_defs.h:166
GPP_B19
#define GPP_B19
Definition:
gpio_soc_defs.h:72
GPP_E17
#define GPP_E17
Definition:
gpio_soc_defs.h:645
GPP_E2
#define GPP_E2
Definition:
gpio_soc_defs.h:630
GPP_C21
#define GPP_C21
Definition:
gpio_soc_defs.h:558
GPP_R2
#define GPP_R2
Definition:
gpio_soc_defs.h:671
GPP_B9
#define GPP_B9
Definition:
gpio_soc_defs.h:62
GPP_F14
#define GPP_F14
Definition:
gpio_soc_defs.h:587
GPP_H3
#define GPP_H3
Definition:
gpio_soc_defs.h:219
GPP_A10
#define GPP_A10
Definition:
gpio_soc_defs.h:129
GPP_A8
#define GPP_A8
Definition:
gpio_soc_defs.h:127
GPP_B11
#define GPP_B11
Definition:
gpio_soc_defs.h:64
GPP_D13
#define GPP_D13
Definition:
gpio_soc_defs.h:265
GPP_B18
#define GPP_B18
Definition:
gpio_soc_defs.h:71
GPP_B5
#define GPP_B5
Definition:
gpio_soc_defs.h:58
GPP_R5
#define GPP_R5
Definition:
gpio_soc_defs.h:674
GPP_F8
#define GPP_F8
Definition:
gpio_soc_defs.h:581
GPP_C19
#define GPP_C19
Definition:
gpio_soc_defs.h:556
GPP_A13
#define GPP_A13
Definition:
gpio_soc_defs.h:132
GPP_S2
#define GPP_S2
Definition:
gpio_soc_defs.h:162
GPP_A21
#define GPP_A21
Definition:
gpio_soc_defs.h:140
GPP_E15
#define GPP_E15
Definition:
gpio_soc_defs.h:643
GPP_B10
#define GPP_B10
Definition:
gpio_soc_defs.h:63
GPP_E16
#define GPP_E16
Definition:
gpio_soc_defs.h:644
GPP_E11
#define GPP_E11
Definition:
gpio_soc_defs.h:639
GPP_F18
#define GPP_F18
Definition:
gpio_soc_defs.h:591
GPP_B3
#define GPP_B3
Definition:
gpio_soc_defs.h:56
GPP_A22
#define GPP_A22
Definition:
gpio_soc_defs.h:141
GPP_F11
#define GPP_F11
Definition:
gpio_soc_defs.h:584
GPP_B21
#define GPP_B21
Definition:
gpio_soc_defs.h:74
GPP_D16
#define GPP_D16
Definition:
gpio_soc_defs.h:268
GPP_A17
#define GPP_A17
Definition:
gpio_soc_defs.h:136
GPP_B17
#define GPP_B17
Definition:
gpio_soc_defs.h:70
GPP_C0
#define GPP_C0
Definition:
gpio_soc_defs.h:537
GPP_E1
#define GPP_E1
Definition:
gpio_soc_defs.h:629
GPP_H8
#define GPP_H8
Definition:
gpio_soc_defs.h:224
GPP_F19
#define GPP_F19
Definition:
gpio_soc_defs.h:592
GPP_B7
#define GPP_B7
Definition:
gpio_soc_defs.h:60
GPP_C7
#define GPP_C7
Definition:
gpio_soc_defs.h:544
GPP_D3
#define GPP_D3
Definition:
gpio_soc_defs.h:255
GPP_R1
#define GPP_R1
Definition:
gpio_soc_defs.h:670
ARRAY_SIZE
#define ARRAY_SIZE(a)
Definition:
helpers.h:12
helpers.h
variant_early_gpio_table
const struct pad_config * variant_early_gpio_table(size_t *num)
Definition:
gpio.c:204
variant_override_gpio_table
const struct pad_config *__weak variant_override_gpio_table(size_t *num)
Definition:
gpio.c:450
override_gpio_table
static const struct pad_config override_gpio_table[]
Definition:
gpio.c:8
early_gpio_table
static const struct pad_config early_gpio_table[]
Definition:
gpio.c:210
NONE
@ NONE
Definition:
qup_se_handlers_common.h:196
PAD_NC
#define PAD_NC(pin)
Definition:
gpio_defs.h:263
PAD_CFG_GPI
#define PAD_CFG_GPI(pad, pull, rst)
Definition:
gpio_defs.h:284
PAD_CFG_GPI_SCI_LOW
#define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig)
Definition:
gpio_defs.h:452
PAD_CFG_NF
#define PAD_CFG_NF(pad, pull, rst, func)
Definition:
gpio_defs.h:197
PAD_CFG_GPI_INT
#define PAD_CFG_GPI_INT(pad, pull, rst, trig)
Definition:
gpio_defs.h:348
PAD_CFG_GPI_APIC
#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv)
Definition:
gpio_defs.h:376
PAD_CFG_GPO
#define PAD_CFG_GPO(pad, val, rst)
Definition:
gpio_defs.h:247
PAD_CFG_GPI_SCI
#define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv)
Definition:
gpio_defs.h:432
PAD_CFG_GPI_GPIO_DRIVER
#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst)
Definition:
gpio_defs.h:323
pad_config
Definition:
gpio.h:75
src
mainboard
google
volteer
variants
volteer
gpio.c
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