coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
com_init.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <bootblock_common.h>
4 #include <device/mmio.h>
5 #include <device/pci_ops.h>
6 #include <soc/gpio.h>
7 #include <soc/lpc.h>
8 #include <soc/pci_devs.h>
9 
11 {
12  uint32_t reg;
13  uint32_t *pad_config_reg;
14 
15  /* Enable the UART hardware for COM1. */
16  reg = 1;
18 
19  /*
20  * Set up the pads to select the UART function
21  * AD12 SW16(UART1_DATAIN/UART0_DATAIN) - Set Mode 2 for UART0_RXD
22  * AD10 SW20(UART1_DATAOUT/UART0_DATAOUT) - Set Mode 2 for UART0_TXD
23  */
26  M2));
27 
30  M2));
31 }
static void write32(void *addr, uint32_t val)
Definition: mmio.h:40
void bootblock_mainboard_early_init(void)
Definition: com_init.c:8
uint32_t * gpio_pad_config_reg(uint8_t community, uint8_t pad)
Definition: gpio_support.c:49
static __always_inline void pci_write_config32(const struct device *dev, u16 reg, u32 val)
Definition: pci_ops.h:76
#define LPC_DEV
Definition: romstage.c:15
#define PCI_DEV(SEGBUS, DEV, FN)
Definition: pci_type.h:14
#define UART_CONT
Definition: lpc.h:16
#define SET_PAD_MODE_SELECTION(pad_config, mode)
Definition: gpio.h:167
@ M2
Definition: gpio.h:384
#define UART1_TXD_PAD
Definition: gpio.h:341
#define UART1_RXD_PAD
Definition: gpio.h:340
#define GP_SOUTHWEST
Definition: gpio.h:28
#define PAD_CONFIG0_DEFAULT0
Definition: gpio.h:199
unsigned int uint32_t
Definition: stdint.h:14