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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <cbmem.h>
#include <romstage_handoff.h>
#include <console/console.h>
#include <device/pci_ops.h>
#include <arch/romstage.h>
#include <northbridge/intel/gm45/gm45.h>
#include <southbridge/intel/i82801ix/i82801ix.h>
#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/common/pmclib.h>
#include <southbridge/intel/common/pmutil.h>
#include <string.h>
Go to the source code of this file.
Macros | |
#define | LPC_DEV PCI_DEV(0, 0x1f, 0) |
#define | MCH_DEV PCI_DEV(0, 0, 0) |
Functions | |
void __weak | mb_setup_superio (void) |
void __weak | mb_pre_raminit_setup (sysinfo_t *sysinfo) |
void __weak | mb_post_raminit_setup (void) |
void | mainboard_romstage_entry (void) |
#define LPC_DEV PCI_DEV(0, 0x1f, 0) |
Definition at line 15 of file romstage.c.
#define MCH_DEV PCI_DEV(0, 0, 0) |
Definition at line 16 of file romstage.c.
Definition at line 33 of file romstage.c.
References BIOS_DEBUG, BIOS_SPEW, cbmem_recovery(), D0F0_DEVEN, D31F0_GEN_PMCON_3, dmibar_clrbits16, sysinfo::enable_igd, sysinfo::enable_peg, device::enabled, enter_raminit_or_reset(), get_gmch_info(), get_mb_spd_addrmap(), gm45_early_init(), gm45_early_reset(), gm45_late_init(), i82801ix_dmi_poll_vc1(), i82801ix_dmi_setup(), i82801ix_early_init(), init_iommu(), init_pm(), LPC_DEV, mainboard_gpio_map, mb_post_raminit_setup(), mb_pre_raminit_setup(), MCH_DEV, mchbar_read16(), mchbar_write16(), memset(), pci_and_config32(), pci_read_config16(), pci_write_config16(), pcidev_on_root(), printk, raminit(), romstage_handoff_init(), setup_pch_gpios(), southbridge_detect_s3_resume(), sysinfo::spd_map, and SSKPD_MCHBAR.
Definition at line 26 of file romstage.c.
Definition at line 22 of file romstage.c.
Definition at line 18 of file romstage.c.