coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Data Structures | |
struct | usb_board_data |
struct | usb_qusb_phy_dig |
struct | usb_qusb_phy_pll |
struct | hs_usb_phy_reg |
Macros | |
#define | PORT_TUNE1_MASK 0xf0 |
#define | POWER_DOWN BIT(0) |
#define | DEBUG_CTRL2_MUX_PLL_LOCK_STATUS 0x4 |
#define | VSTATUS_PLL_LOCK_STATUS_MASK BIT(0) |
#define | QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x03 |
#define | QUSB2PHY_PLL_CLOCK_INVERTERS 0x7c |
#define | QUSB2PHY_PLL_CMODE 0x80 |
#define | QUSB2PHY_PLL_LOCK_DELAY 0x0a |
#define | QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0x19 |
#define | QUSB2PHY_PLL_BIAS_CONTROL_1 0x40 |
#define | QUSB2PHY_PLL_BIAS_CONTROL_2 0x22 |
#define | QUSB2PHY_PWR_CTRL2 0x21 |
#define | QUSB2PHY_IMP_CTRL1 0x08 |
#define | QUSB2PHY_IMP_CTRL2 0x58 |
#define | QUSB2PHY_PORT_TUNE1 0xc5 |
#define | QUSB2PHY_PORT_TUNE2 0x29 |
#define | QUSB2PHY_PORT_TUNE3 0xca |
#define | QUSB2PHY_PORT_TUNE4 0x04 |
#define | QUSB2PHY_PORT_TUNE5 0x03 |
#define | QUSB2PHY_CHG_CTRL2 0x30 |
#define | QFPROM_BASE 0x00780000 |
#define | QUSB_PRIM_PHY_BASE 0x088e3000 |
#define | QUSB_PRIM_PHY_DIG_BASE 0x088e3200 |
#define | HS_USB_PRIM_PHY_BASE QUSB_PRIM_PHY_BASE |
Functions | |
check_member (usb_qusb_phy_dig, tune5, 0x50) | |
check_member (usb_qusb_phy_dig, debug_ctrl2, 0x80) | |
check_member (usb_qusb_phy_dig, debug_stat5, 0xA0) | |
check_member (usb_qusb_phy_pll, cmode, 0x2C) | |
check_member (usb_qusb_phy_pll, bias_ctrl_2, 0x198) | |
check_member (usb_qusb_phy_pll, dig_tim, 0xB4) | |
#define DEBUG_CTRL2_MUX_PLL_LOCK_STATUS 0x4 |
Definition at line 12 of file qusb_phy.h.
#define HS_USB_PRIM_PHY_BASE QUSB_PRIM_PHY_BASE |
Definition at line 40 of file qusb_phy.h.
#define PORT_TUNE1_MASK 0xf0 |
Definition at line 6 of file qusb_phy.h.
#define POWER_DOWN BIT(0) |
Definition at line 9 of file qusb_phy.h.
#define QFPROM_BASE 0x00780000 |
Definition at line 36 of file qusb_phy.h.
#define QUSB2PHY_CHG_CTRL2 0x30 |
Definition at line 33 of file qusb_phy.h.
#define QUSB2PHY_IMP_CTRL1 0x08 |
Definition at line 26 of file qusb_phy.h.
#define QUSB2PHY_IMP_CTRL2 0x58 |
Definition at line 27 of file qusb_phy.h.
#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x03 |
Definition at line 18 of file qusb_phy.h.
#define QUSB2PHY_PLL_BIAS_CONTROL_1 0x40 |
Definition at line 23 of file qusb_phy.h.
#define QUSB2PHY_PLL_BIAS_CONTROL_2 0x22 |
Definition at line 24 of file qusb_phy.h.
#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x7c |
Definition at line 19 of file qusb_phy.h.
#define QUSB2PHY_PLL_CMODE 0x80 |
Definition at line 20 of file qusb_phy.h.
#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0x19 |
Definition at line 22 of file qusb_phy.h.
#define QUSB2PHY_PLL_LOCK_DELAY 0x0a |
Definition at line 21 of file qusb_phy.h.
#define QUSB2PHY_PORT_TUNE1 0xc5 |
Definition at line 28 of file qusb_phy.h.
#define QUSB2PHY_PORT_TUNE2 0x29 |
Definition at line 29 of file qusb_phy.h.
#define QUSB2PHY_PORT_TUNE3 0xca |
Definition at line 30 of file qusb_phy.h.
#define QUSB2PHY_PORT_TUNE4 0x04 |
Definition at line 31 of file qusb_phy.h.
#define QUSB2PHY_PORT_TUNE5 0x03 |
Definition at line 32 of file qusb_phy.h.
#define QUSB2PHY_PWR_CTRL2 0x21 |
Definition at line 25 of file qusb_phy.h.
#define QUSB_PRIM_PHY_BASE 0x088e3000 |
Definition at line 37 of file qusb_phy.h.
#define QUSB_PRIM_PHY_DIG_BASE 0x088e3200 |
Definition at line 38 of file qusb_phy.h.
#define VSTATUS_PLL_LOCK_STATUS_MASK BIT(0) |
Definition at line 15 of file qusb_phy.h.
check_member | ( | usb_qusb_phy_dig | , |
debug_ctrl2 | , | ||
0x80 | |||
) |
check_member | ( | usb_qusb_phy_dig | , |
debug_stat5 | , | ||
0xA0 | |||
) |
check_member | ( | usb_qusb_phy_dig | , |
tune5 | , | ||
0x50 | |||
) |
check_member | ( | usb_qusb_phy_pll | , |
bias_ctrl_2 | , | ||
0x198 | |||
) |
check_member | ( | usb_qusb_phy_pll | , |
cmode | , | ||
0x2C | |||
) |
check_member | ( | usb_qusb_phy_pll | , |
dig_tim | , | ||
0xB4 | |||
) |