coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
early_init.c
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <
bootblock_common.h
>
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#include <
southbridge/intel/i82801jx/i82801jx.h
>
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#include <
northbridge/intel/x4x/x4x.h
>
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#include <
superio/ite/common/ite.h
>
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#include <
superio/ite/it8720f/it8720f.h
>
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#define GPIO_DEV PNP_DEV(0x2e, IT8720F_GPIO)
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void
bootblock_mainboard_early_init
(
void
)
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{
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/* Set up GPIOs on Super I/O. */
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ite_reg_write
(
GPIO_DEV
, 0x25, 0x00);
// GPIO set 1
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ite_reg_write
(
GPIO_DEV
, 0x26, 0x0c);
// GPIO set 2
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ite_reg_write
(
GPIO_DEV
, 0x27, 0x70);
// GPIO set 3
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ite_reg_write
(
GPIO_DEV
, 0x28, 0x40);
// GPIO set 4
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ite_reg_write
(
GPIO_DEV
, 0x29, 0x00);
// GPIO set 5
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/* Enable 3VSB during Suspend-to-RAM */
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ite_enable_3vsbsw
(
GPIO_DEV
);
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/* Delay PWROK2 after 3VSBSW# during resume from Suspend-to-RAM */
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ite_delay_pwrgd3
(
GPIO_DEV
);
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}
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void
mb_get_spd_map
(
u8
spd_map[4])
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{
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spd_map[0] = 0x50;
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spd_map[1] = 0x51;
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spd_map[2] = 0x52;
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spd_map[3] = 0x53;
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}
bootblock_common.h
i82801jx.h
it8720f.h
ite_delay_pwrgd3
void ite_delay_pwrgd3(pnp_devfn_t dev)
Definition:
early_serial.c:112
ite_reg_write
void ite_reg_write(pnp_devfn_t dev, u8 reg, u8 value)
Definition:
early_serial.c:41
ite_enable_3vsbsw
void ite_enable_3vsbsw(pnp_devfn_t dev)
Definition:
early_serial.c:85
ite.h
bootblock_mainboard_early_init
void bootblock_mainboard_early_init(void)
Definition:
early_init.c:11
GPIO_DEV
#define GPIO_DEV
Definition:
early_init.c:9
mb_get_spd_map
void mb_get_spd_map(u8 spd_map[4])
Definition:
early_init.c:27
u8
uint8_t u8
Definition:
stdint.h:45
x4x.h
src
mainboard
acer
g43t-am3
early_init.c
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