coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
Macros | Functions
x4x.h File Reference
#include <stdint.h>
#include "memmap.h"
#include "registers/host_bridge.h"
#include <northbridge/intel/common/fixed_bars.h>
#include <device/device.h>
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Macros

#define BOOT_PATH_NORMAL   0
 
#define BOOT_PATH_WARM_RESET   1
 
#define BOOT_PATH_RESUME   2
 
#define HOST_BRIDGE   PCI_DEV(0, 0, 0)
 
#define PEG_CAP   0xa2
 
#define SLOTCAP   0xb4
 
#define PEGLC   0xec
 
#define D1F0_VCCAP   0x104
 
#define D1F0_VC0RCTL   0x114
 
#define GCFGC_PCIDEV   PCI_DEV(0, 2, 0)
 
#define GCFGC_OFFSET   0xf0
 
#define GCFGC_CR_SHIFT   0
 
#define GCFGC_CR_MASK   (0xf << GCFGC_CR_SHIFT)
 
#define GCFGC_CS_SHIFT   8
 
#define GCFGC_CS_MASK   (0xf << GCFGC_CS_SHIFT)
 
#define GCFGC_CD_SHIFT   12
 
#define GCFGC_CD_MASK   (0x1 << GCFGC_CD_SHIFT)
 
#define GCFGC_UPDATE_SHIFT   5
 
#define GCFGC_UPDATE   (0x1 << GCFGC_UPDATE_SHIFT)
 
#define CHDECMISC   0x111
 
#define STACKED_MEM   (1 << 1)
 
#define C0DRB0   0x200
 
#define C0DRB1   0x202
 
#define C0DRB2   0x204
 
#define C0DRB3   0x206
 
#define C0DRA01   0x208
 
#define C0DRA23   0x20a
 
#define C0CKECTRL   0x260
 
#define C1DRB0   0x600
 
#define C1DRB1   0x602
 
#define C1DRB2   0x604
 
#define C1DRB3   0x606
 
#define C1DRA01   0x608
 
#define C1DRA23   0x60a
 
#define C1CKECTRL   0x660
 
#define PMSTS_MCHBAR   0x0f14 /* Self refresh channel status */
 
#define PMSTS_WARM_RESET   (1 << 8)
 
#define PMSTS_BOTH_SELFREFRESH   (3 << 0)
 
#define CLKCFG_MCHBAR   0x0c00
 
#define CLKCFG_FSBCLK_SHIFT   0
 
#define CLKCFG_FSBCLK_MASK   (7 << CLKCFG_FSBCLK_SHIFT)
 
#define CLKCFG_MEMCLK_SHIFT   4
 
#define CLKCFG_MEMCLK_MASK   (7 << CLKCFG_MEMCLK_SHIFT)
 
#define CLKCFG_UPDATE   (1 << 10)
 
#define SSKPD_MCHBAR   0x0c20 /* 64 bit */
 
#define DMIVCECH   0x000 /* 32bit */
 
#define DMIPVCCAP1   0x004 /* 32bit */
 
#define DMIVC0RCAP   0x010 /* 32bit */
 
#define DMIVC0RCTL   0x014 /* 32bit */
 
#define DMIVC0RSTS   0x01a /* 16bit */
 
#define VC0NP   (1 << 1)
 
#define DMIVC1RCAP   0x01c /* 32bit */
 
#define DMIVC1RCTL   0x020 /* 32bit */
 
#define DMIVC1RSTS   0x026 /* 16bit */
 
#define VC1NP   (1 << 1)
 
#define DMIVCPRCAP   0x028 /* 32bit */
 
#define DMIVCPRCTL   0x02c /* 32bit */
 
#define DMIVCPRSTS   0x032 /* 16bit */
 
#define VCPNP   (1 << 1)
 
#define DMIVCMRCAP   0x034 /* 32bit */
 
#define DMIVCMRCTL   0x038 /* 32bit */
 
#define DMIVCMRSTS   0x03e /* 16bit */
 
#define VCMNP   (1 << 1)
 
#define DMIESD   0x044 /* 32bit */
 
#define DMILE1D   0x050 /* 32bit */
 
#define DMILE1A   0x058 /* 64bit */
 
#define DMILE2D   0x060 /* 32bit */
 
#define DMILE2A   0x068 /* 64bit */
 
#define DMILCAP   0x084 /* 32bit */
 
#define DMILCTL   0x088 /* 16bit */
 
#define DMILSTS   0x08a /* 16bit */
 
#define DMIUESTS   0x1c4 /* 32bit */
 
#define DMICESTS   0x1d0 /* 32bit */
 
#define EPPVCCAP1   0x004 /* 32bit */
 
#define EPPVCCTL   0x00c /* 32bit */
 
#define EPVC0RCAP   0x010 /* 32bit */
 
#define EPVC0RCTL   0x014 /* 32bit */
 
#define EPVC0RSTS   0x01a /* 16bit */
 
#define EPVC1RCAP   0x01c /* 32bit */
 
#define EPVC1RCTL   0x020 /* 32bit */
 
#define EPVC1RSTS   0x026 /* 16bit */
 
#define EPVC1MTS   0x028 /* 32bit */
 
#define EPVC1ITC   0x02c /* 32bit */
 
#define EPESD   0x044 /* 32bit */
 
#define EPLE1D   0x050 /* 32bit */
 
#define EPLE1A   0x058 /* 64bit */
 
#define EPLE2D   0x060 /* 32bit */
 
#define EPLE2A   0x068 /* 64bit */
 
#define EP_PORTARB(x)   (0x100 + 4 * (x)) /* 256bit */
 

Functions

void x4x_early_init (void)
 
void x4x_late_init (void)
 
void mb_get_spd_map (u8 spd_map[4])
 
void mb_pre_raminit_setup (int s3_resume)
 
u32 decode_igd_memory_size (u32 gms)
 Decodes used Graphics Mode Select (GMS) to kilobytes. More...
 
u32 decode_igd_gtt_size (u32 gsm)
 Decodes used Graphics Stolen Memory (GSM) to kilobytes. More...
 
u32 decode_tseg_size (const u32 esmramc)
 Decodes used TSEG size to bytes. More...
 
unsigned long northbridge_write_acpi_tables (const struct device *device, unsigned long start, struct acpi_rsdp *rsdp)
 

Macro Definition Documentation

◆ BOOT_PATH_NORMAL

#define BOOT_PATH_NORMAL   0

Definition at line 9 of file x4x.h.

◆ BOOT_PATH_RESUME

#define BOOT_PATH_RESUME   2

Definition at line 11 of file x4x.h.

◆ BOOT_PATH_WARM_RESET

#define BOOT_PATH_WARM_RESET   1

Definition at line 10 of file x4x.h.

◆ C0CKECTRL

#define C0CKECTRL   0x260

Definition at line 58 of file x4x.h.

◆ C0DRA01

#define C0DRA01   0x208

Definition at line 56 of file x4x.h.

◆ C0DRA23

#define C0DRA23   0x20a

Definition at line 57 of file x4x.h.

◆ C0DRB0

#define C0DRB0   0x200

Definition at line 52 of file x4x.h.

◆ C0DRB1

#define C0DRB1   0x202

Definition at line 53 of file x4x.h.

◆ C0DRB2

#define C0DRB2   0x204

Definition at line 54 of file x4x.h.

◆ C0DRB3

#define C0DRB3   0x206

Definition at line 55 of file x4x.h.

◆ C1CKECTRL

#define C1CKECTRL   0x660

Definition at line 66 of file x4x.h.

◆ C1DRA01

#define C1DRA01   0x608

Definition at line 64 of file x4x.h.

◆ C1DRA23

#define C1DRA23   0x60a

Definition at line 65 of file x4x.h.

◆ C1DRB0

#define C1DRB0   0x600

Definition at line 60 of file x4x.h.

◆ C1DRB1

#define C1DRB1   0x602

Definition at line 61 of file x4x.h.

◆ C1DRB2

#define C1DRB2   0x604

Definition at line 62 of file x4x.h.

◆ C1DRB3

#define C1DRB3   0x606

Definition at line 63 of file x4x.h.

◆ CHDECMISC

#define CHDECMISC   0x111

Definition at line 49 of file x4x.h.

◆ CLKCFG_FSBCLK_MASK

#define CLKCFG_FSBCLK_MASK   (7 << CLKCFG_FSBCLK_SHIFT)

Definition at line 74 of file x4x.h.

◆ CLKCFG_FSBCLK_SHIFT

#define CLKCFG_FSBCLK_SHIFT   0

Definition at line 73 of file x4x.h.

◆ CLKCFG_MCHBAR

#define CLKCFG_MCHBAR   0x0c00

Definition at line 72 of file x4x.h.

◆ CLKCFG_MEMCLK_MASK

#define CLKCFG_MEMCLK_MASK   (7 << CLKCFG_MEMCLK_SHIFT)

Definition at line 76 of file x4x.h.

◆ CLKCFG_MEMCLK_SHIFT

#define CLKCFG_MEMCLK_SHIFT   4

Definition at line 75 of file x4x.h.

◆ CLKCFG_UPDATE

#define CLKCFG_UPDATE   (1 << 10)

Definition at line 77 of file x4x.h.

◆ D1F0_VC0RCTL

#define D1F0_VC0RCTL   0x114

Definition at line 27 of file x4x.h.

◆ D1F0_VCCAP

#define D1F0_VCCAP   0x104

Definition at line 26 of file x4x.h.

◆ DMICESTS

#define DMICESTS   0x1d0 /* 32bit */

Definition at line 120 of file x4x.h.

◆ DMIESD

#define DMIESD   0x044 /* 32bit */

Definition at line 108 of file x4x.h.

◆ DMILCAP

#define DMILCAP   0x084 /* 32bit */

Definition at line 115 of file x4x.h.

◆ DMILCTL

#define DMILCTL   0x088 /* 16bit */

Definition at line 116 of file x4x.h.

◆ DMILE1A

#define DMILE1A   0x058 /* 64bit */

Definition at line 111 of file x4x.h.

◆ DMILE1D

#define DMILE1D   0x050 /* 32bit */

Definition at line 110 of file x4x.h.

◆ DMILE2A

#define DMILE2A   0x068 /* 64bit */

Definition at line 113 of file x4x.h.

◆ DMILE2D

#define DMILE2D   0x060 /* 32bit */

Definition at line 112 of file x4x.h.

◆ DMILSTS

#define DMILSTS   0x08a /* 16bit */

Definition at line 117 of file x4x.h.

◆ DMIPVCCAP1

#define DMIPVCCAP1   0x004 /* 32bit */

Definition at line 86 of file x4x.h.

◆ DMIUESTS

#define DMIUESTS   0x1c4 /* 32bit */

Definition at line 119 of file x4x.h.

◆ DMIVC0RCAP

#define DMIVC0RCAP   0x010 /* 32bit */

Definition at line 88 of file x4x.h.

◆ DMIVC0RCTL

#define DMIVC0RCTL   0x014 /* 32bit */

Definition at line 89 of file x4x.h.

◆ DMIVC0RSTS

#define DMIVC0RSTS   0x01a /* 16bit */

Definition at line 90 of file x4x.h.

◆ DMIVC1RCAP

#define DMIVC1RCAP   0x01c /* 32bit */

Definition at line 93 of file x4x.h.

◆ DMIVC1RCTL

#define DMIVC1RCTL   0x020 /* 32bit */

Definition at line 94 of file x4x.h.

◆ DMIVC1RSTS

#define DMIVC1RSTS   0x026 /* 16bit */

Definition at line 95 of file x4x.h.

◆ DMIVCECH

#define DMIVCECH   0x000 /* 32bit */

Definition at line 85 of file x4x.h.

◆ DMIVCMRCAP

#define DMIVCMRCAP   0x034 /* 32bit */

Definition at line 103 of file x4x.h.

◆ DMIVCMRCTL

#define DMIVCMRCTL   0x038 /* 32bit */

Definition at line 104 of file x4x.h.

◆ DMIVCMRSTS

#define DMIVCMRSTS   0x03e /* 16bit */

Definition at line 105 of file x4x.h.

◆ DMIVCPRCAP

#define DMIVCPRCAP   0x028 /* 32bit */

Definition at line 98 of file x4x.h.

◆ DMIVCPRCTL

#define DMIVCPRCTL   0x02c /* 32bit */

Definition at line 99 of file x4x.h.

◆ DMIVCPRSTS

#define DMIVCPRSTS   0x032 /* 16bit */

Definition at line 100 of file x4x.h.

◆ EP_PORTARB

#define EP_PORTARB (   x)    (0x100 + 4 * (x)) /* 256bit */

Definition at line 147 of file x4x.h.

◆ EPESD

#define EPESD   0x044 /* 32bit */

Definition at line 140 of file x4x.h.

◆ EPLE1A

#define EPLE1A   0x058 /* 64bit */

Definition at line 143 of file x4x.h.

◆ EPLE1D

#define EPLE1D   0x050 /* 32bit */

Definition at line 142 of file x4x.h.

◆ EPLE2A

#define EPLE2A   0x068 /* 64bit */

Definition at line 145 of file x4x.h.

◆ EPLE2D

#define EPLE2D   0x060 /* 32bit */

Definition at line 144 of file x4x.h.

◆ EPPVCCAP1

#define EPPVCCAP1   0x004 /* 32bit */

Definition at line 126 of file x4x.h.

◆ EPPVCCTL

#define EPPVCCTL   0x00c /* 32bit */

Definition at line 127 of file x4x.h.

◆ EPVC0RCAP

#define EPVC0RCAP   0x010 /* 32bit */

Definition at line 129 of file x4x.h.

◆ EPVC0RCTL

#define EPVC0RCTL   0x014 /* 32bit */

Definition at line 130 of file x4x.h.

◆ EPVC0RSTS

#define EPVC0RSTS   0x01a /* 16bit */

Definition at line 131 of file x4x.h.

◆ EPVC1ITC

#define EPVC1ITC   0x02c /* 32bit */

Definition at line 138 of file x4x.h.

◆ EPVC1MTS

#define EPVC1MTS   0x028 /* 32bit */

Definition at line 137 of file x4x.h.

◆ EPVC1RCAP

#define EPVC1RCAP   0x01c /* 32bit */

Definition at line 133 of file x4x.h.

◆ EPVC1RCTL

#define EPVC1RCTL   0x020 /* 32bit */

Definition at line 134 of file x4x.h.

◆ EPVC1RSTS

#define EPVC1RSTS   0x026 /* 16bit */

Definition at line 135 of file x4x.h.

◆ GCFGC_CD_MASK

#define GCFGC_CD_MASK   (0x1 << GCFGC_CD_SHIFT)

Definition at line 39 of file x4x.h.

◆ GCFGC_CD_SHIFT

#define GCFGC_CD_SHIFT   12

Definition at line 38 of file x4x.h.

◆ GCFGC_CR_MASK

#define GCFGC_CR_MASK   (0xf << GCFGC_CR_SHIFT)

Definition at line 35 of file x4x.h.

◆ GCFGC_CR_SHIFT

#define GCFGC_CR_SHIFT   0

Definition at line 34 of file x4x.h.

◆ GCFGC_CS_MASK

#define GCFGC_CS_MASK   (0xf << GCFGC_CS_SHIFT)

Definition at line 37 of file x4x.h.

◆ GCFGC_CS_SHIFT

#define GCFGC_CS_SHIFT   8

Definition at line 36 of file x4x.h.

◆ GCFGC_OFFSET

#define GCFGC_OFFSET   0xf0

Definition at line 33 of file x4x.h.

◆ GCFGC_PCIDEV

#define GCFGC_PCIDEV   PCI_DEV(0, 2, 0)

Definition at line 32 of file x4x.h.

◆ GCFGC_UPDATE

#define GCFGC_UPDATE   (0x1 << GCFGC_UPDATE_SHIFT)

Definition at line 41 of file x4x.h.

◆ GCFGC_UPDATE_SHIFT

#define GCFGC_UPDATE_SHIFT   5

Definition at line 40 of file x4x.h.

◆ HOST_BRIDGE

#define HOST_BRIDGE   PCI_DEV(0, 0, 0)

Definition at line 16 of file x4x.h.

◆ PEG_CAP

#define PEG_CAP   0xa2

Definition at line 23 of file x4x.h.

◆ PEGLC

#define PEGLC   0xec

Definition at line 25 of file x4x.h.

◆ PMSTS_BOTH_SELFREFRESH

#define PMSTS_BOTH_SELFREFRESH   (3 << 0)

Definition at line 70 of file x4x.h.

◆ PMSTS_MCHBAR

#define PMSTS_MCHBAR   0x0f14 /* Self refresh channel status */

Definition at line 68 of file x4x.h.

◆ PMSTS_WARM_RESET

#define PMSTS_WARM_RESET   (1 << 8)

Definition at line 69 of file x4x.h.

◆ SLOTCAP

#define SLOTCAP   0xb4

Definition at line 24 of file x4x.h.

◆ SSKPD_MCHBAR

#define SSKPD_MCHBAR   0x0c20 /* 64 bit */

Definition at line 79 of file x4x.h.

◆ STACKED_MEM

#define STACKED_MEM   (1 << 1)

Definition at line 50 of file x4x.h.

◆ VC0NP

#define VC0NP   (1 << 1)

Definition at line 91 of file x4x.h.

◆ VC1NP

#define VC1NP   (1 << 1)

Definition at line 96 of file x4x.h.

◆ VCMNP

#define VCMNP   (1 << 1)

Definition at line 106 of file x4x.h.

◆ VCPNP

#define VCPNP   (1 << 1)

Definition at line 101 of file x4x.h.

Function Documentation

◆ decode_igd_gtt_size()

u32 decode_igd_gtt_size ( const u32  gsm)

Decodes used Graphics Stolen Memory (GSM) to kilobytes.

Decodes used Graphics Stolen Memory (GSM) to kilobytes.

Definition at line 36 of file memmap.c.

References ARRAY_SIZE, BIOS_DEBUG, die(), and printk.

Referenced by northbridge_get_tseg_base().

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◆ decode_igd_memory_size()

u32 decode_igd_memory_size ( u32  gms)

Decodes used Graphics Mode Select (GMS) to kilobytes.

Definition at line 24 of file memmap.c.

References ARRAY_SIZE, BIOS_DEBUG, die(), and printk.

Referenced by northbridge_get_tseg_base().

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◆ decode_tseg_size()

u32 decode_tseg_size ( const u32  esmramc)

Decodes used TSEG size to bytes.

Definition at line 41 of file memmap.c.

References die().

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◆ mb_get_spd_map()

void mb_get_spd_map ( u8  spd_map[4])

Definition at line 27 of file early_init.c.

References CONFIG.

Referenced by perform_raminit().

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◆ mb_pre_raminit_setup()

void mb_pre_raminit_setup ( int  s3_resume)

Definition at line 95 of file early_init.c.

References BIOS_DEBUG, full_reset(), printk, and setup_sio_gpio().

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◆ northbridge_write_acpi_tables()

unsigned long northbridge_write_acpi_tables ( const struct device *  device,
unsigned long  start,
struct acpi_rsdp *  rsdp 
)

Definition at line 56 of file acpi.c.

◆ x4x_early_init()

void x4x_early_init ( void  )

Definition at line 14 of file early_init.c.

References BOARD_DEVEN, D0EN, D0F0_CAPID0, D0F0_DEVEN, D0F0_DMIBAR_LO, D0F0_EPBAR_LO, D0F0_GGC, D0F0_MCHBAR_LO, D0F0_PAM, D1EN, DEFAULT_HECIBAR, get_uint_option(), HOST_BRIDGE, PCI_DEV, pci_read_config32(), pci_write_config16(), pci_write_config32(), pci_write_config8(), and PEG1EN.

Referenced by mainboard_romstage_entry().

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◆ x4x_late_init()

void x4x_late_init ( void  )

Definition at line 217 of file early_init.c.

References init_dmi(), and init_egress().

Referenced by mainboard_romstage_entry().

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