coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
mptable.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <device/device.h>
4 #include <arch/smp/mpspec.h>
5 #include <arch/ioapic.h>
6 
7 static void *smp_write_config_table(void *v)
8 {
9  struct mp_config_table *mc;
10  int isa_bus;
11 
12  mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
13 
14  mptable_init(mc);
15 
17 
18  mptable_write_buses(mc, NULL, &isa_bus);
19 
20  /* I/O APICs: APIC ID Version State Address */
22 
23  /* Legacy Interrupts */
24  mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
25 
28  smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x01, 0x00, ioapic_id, 0x10); /* PCIe root 0.01.0 */
29  smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x02, 0x00, ioapic_id, 0x10); /* VGA 0.02.0 */
30  smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1b, 0x00, ioapic_id, 0x16); /* HD Audio 0:1b.0 */
31  smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x00, ioapic_id, 0x11); /* PCIe 0:1c.0 */
32  smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x01, ioapic_id, 0x10); /* PCIe 0:1c.1 */
33  smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x02, ioapic_id, 0x12); /* PCIe 0:1c.2 */
34  smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x03, ioapic_id, 0x13); /* PCIe 0:1c.3 */
35  smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x00, ioapic_id, 0x15); /* USB 0:1d.0 */
36  smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x01, ioapic_id, 0x13); /* USB 0:1d.1 */
37  smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x02, ioapic_id, 0x12); /* USB 0:1d.2 */
38  smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x03, ioapic_id, 0x10); /* USB 0:1d.3 */
39  smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x00, ioapic_id, 0x12); /* LPC 0:1f.0 */
40  smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x01, ioapic_id, 0x13); /* IDE 0:1f.1 */
41  smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x03, ioapic_id, 0x10); /* SATA 0:1f.3 */
42  smp_write_pci_intsrc(mc, mp_INT, 0x03, 0x03, 0x00, ioapic_id, 0x13); /* Firewire 3:03.0 */
43 
44  mptable_lintsrc(mc, isa_bus);
45  return mptable_finalize(mc);
46 }
47 
48 unsigned long write_smp_table(unsigned long addr)
49 {
50  void *v;
52  return (unsigned long)smp_write_config_table(v);
53 }
unsigned long write_smp_table(unsigned long addr)
Definition: mptable.c:48
static void * smp_write_config_table(void *v)
Definition: mptable.c:7
#define VIO_APIC_VADDR
Definition: ioapic.h:7
static u32 addr
Definition: cirrus.c:14
#define MP_IRQ_TRIGGER_DEFAULT
Definition: mpspec.h:127
void * smp_write_floating_table(unsigned long addr, unsigned int virtualwire)
Definition: mpspec.c:84
#define MP_APIC_ALL
Definition: mpspec.h:139
@ mp_NMI
Definition: mpspec.h:118
@ mp_INT
Definition: mpspec.h:117
@ mp_ExtINT
Definition: mpspec.h:120
void smp_write_intsrc(struct mp_config_table *mc, u8 irqtype, u16 irqflag, u8 srcbus, u8 srcbusirq, u8 dstapic, u8 dstirq)
Definition: mpspec.c:237
#define MP_IRQ_POLARITY_LOW
Definition: mpspec.h:125
void * mptable_finalize(struct mp_config_table *mc)
Definition: mpspec.c:504
void mptable_lintsrc(struct mp_config_table *mc, unsigned long bus_isa)
Definition: mpspec.c:418
void mptable_init(struct mp_config_table *mc)
Definition: mpspec.c:14
#define SMP_FLOATING_TABLE_LEN
Definition: mpspec.h:26
void smp_write_processors(struct mp_config_table *mc)
Definition: mpspec.c:146
#define MP_IRQ_POLARITY_DEFAULT
Definition: mpspec.h:123
u8 smp_write_ioapic_from_hw(struct mp_config_table *mc, void *apicaddr)
Definition: mpspec.c:224
#define MP_IRQ_TRIGGER_LEVEL
Definition: mpspec.h:129
void mptable_write_buses(struct mp_config_table *mc, int *max_pci_bus, int *isa_bus)
Definition: mpspec.c:465
void smp_write_pci_intsrc(struct mp_config_table *mc, u8 irqtype, u8 srcbus, u8 dev, u8 pirq, u8 dstapic, u8 dstirq)
Definition: mpspec.c:264
void mptable_add_isa_interrupts(struct mp_config_table *mc, unsigned long bus_isa, unsigned long apicid, int external)
Definition: mpspec.c:426
#define NULL
Definition: stddef.h:19
uint8_t u8
Definition: stdint.h:45