coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
ramstage.c
Go to the documentation of this file.
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <console/console.h>
4 #include <soc/ramstage.h>
5 #include <soc/smbus.h>
6 #include "cpld.h"
7 
8 struct edp_data {
9  u8 payload_length;
10  u8 address;
11  /* data: reg[15:8],reg[7:0], data bytes starting with data[7:0] */
12  u8 data[6];
13 } __packed;
14 
15 static const struct edp_data b101uan01_table[] = {
16  /* set eDP bridge to 1200x1920 */
17  /* IO */
18  {6, 0x68, {0x08, 0x00, 0x01, 0x00, 0x00, 0x00} },
19  /* Boot */
20  {6, 0x68, {0x10, 0x00, 0x78, 0x69, 0x00, 0x00} },
21  {6, 0x68, {0x10, 0x04, 0x02, 0x08, 0x02, 0x00} },
22  {6, 0x68, {0x10, 0x08, 0x23, 0x00, 0x87, 0x02} },
23  {6, 0x68, {0x10, 0x0C, 0x19, 0x04, 0x00, 0x23} },
24  {6, 0x68, {0x10, 0x10, 0x06, 0x00, 0x67, 0x00} },
25  {6, 0x68, {0x10, 0x14, 0x01, 0x00, 0x00, 0x00} },
26  {6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF} },
27  /* Internal */
28  {3, 0x68, {0xB0, 0x05, 0x0A, 0x00, 0x00, 0x00} },
29  {3, 0x68, {0xB0, 0x06, 0x03, 0x00, 0x00, 0x00} },
30  {3, 0x68, {0xB0, 0x07, 0x16, 0x00, 0x00, 0x00} },
31  {3, 0x68, {0xB0, 0x08, 0x00, 0x00, 0x00, 0x00} },
32  {3, 0x68, {0xB0, 0x09, 0x21, 0x00, 0x00, 0x00} },
33  {3, 0x68, {0xB0, 0x0A, 0x07, 0x00, 0x00, 0x00} },
34  {6, 0x68, {0x10, 0x14, 0x03, 0x00, 0x00, 0x00} },
35  {6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF} },
36  /* eDP */
37  {3, 0x68, {0x80, 0x03, 0x41, 0x00, 0x00, 0x00} },
38  {3, 0x68, {0xB4, 0x00, 0x0D, 0x00, 0x00, 0x00} },
39  /* DPRX */
40  {3, 0x68, {0xB8, 0x8E, 0xFF, 0x00, 0x00, 0x00} },
41  {3, 0x68, {0xB8, 0x8F, 0xFF, 0x00, 0x00, 0x00} },
42  {3, 0x68, {0xB8, 0x9A, 0xFF, 0x00, 0x00, 0x00} },
43  {3, 0x68, {0xB8, 0x9B, 0xFF, 0x00, 0x00, 0x00} },
44  {3, 0x68, {0xB8, 0x00, 0x0E, 0x00, 0x00, 0x00} },
45  {3, 0x68, {0xBB, 0x26, 0x02, 0x00, 0x00, 0x00} },
46  {3, 0x68, {0xBB, 0x01, 0x20, 0x00, 0x00, 0x00} },
47  {3, 0x68, {0xB8, 0xC0, 0xF1, 0x00, 0x00, 0x00} },
48  {3, 0x68, {0xB8, 0xC1, 0xF1, 0x00, 0x00, 0x00} },
49  {3, 0x68, {0xB8, 0xC2, 0xF0, 0x00, 0x00, 0x00} },
50  {3, 0x68, {0xB8, 0xC3, 0xF0, 0x00, 0x00, 0x00} },
51  {3, 0x68, {0xB8, 0xC4, 0xF0, 0x00, 0x00, 0x00} },
52  {3, 0x68, {0xB8, 0xC5, 0xF0, 0x00, 0x00, 0x00} },
53  {3, 0x68, {0xB8, 0xC6, 0xF0, 0x00, 0x00, 0x00} },
54  {3, 0x68, {0xB8, 0xC7, 0xF0, 0x00, 0x00, 0x00} },
55  {3, 0x68, {0xB8, 0x0B, 0x00, 0x00, 0x00, 0x00} },
56  {3, 0x68, {0xB8, 0x33, 0x00, 0x00, 0x00, 0x00} },
57  {3, 0x68, {0xB8, 0x5B, 0x00, 0x00, 0x00, 0x00} },
58  {3, 0x68, {0xB8, 0x10, 0x00, 0x00, 0x00, 0x00} },
59  {3, 0x68, {0xB8, 0x38, 0x00, 0x00, 0x00, 0x00} },
60  {3, 0x68, {0xB8, 0x60, 0x00, 0x00, 0x00, 0x00} },
61  {3, 0x68, {0xB8, 0x15, 0x00, 0x00, 0x00, 0x00} },
62  {3, 0x68, {0xB8, 0x3D, 0x00, 0x00, 0x00, 0x00} },
63  {3, 0x68, {0xB8, 0x65, 0x00, 0x00, 0x00, 0x00} },
64  {3, 0x68, {0xB8, 0x1A, 0x00, 0x00, 0x00, 0x00} },
65  {3, 0x68, {0xB8, 0x42, 0x00, 0x00, 0x00, 0x00} },
66  {3, 0x68, {0xB8, 0x6A, 0x00, 0x00, 0x00, 0x00} },
67  {3, 0x68, {0xB8, 0x1F, 0x00, 0x00, 0x00, 0x00} },
68  {3, 0x68, {0xB8, 0x47, 0x00, 0x00, 0x00, 0x00} },
69  {3, 0x68, {0xB8, 0x6F, 0x00, 0x00, 0x00, 0x00} },
70  {3, 0x68, {0xB8, 0x24, 0x00, 0x00, 0x00, 0x00} },
71  {3, 0x68, {0xB8, 0x4C, 0x00, 0x00, 0x00, 0x00} },
72  {3, 0x68, {0xB8, 0x74, 0x00, 0x00, 0x00, 0x00} },
73  {3, 0x68, {0xB8, 0x29, 0x00, 0x00, 0x00, 0x00} },
74  {3, 0x68, {0xB8, 0x51, 0x00, 0x00, 0x00, 0x00} },
75  {3, 0x68, {0xB8, 0x79, 0x00, 0x00, 0x00, 0x00} },
76  {3, 0x68, {0xB8, 0x2E, 0x00, 0x00, 0x00, 0x00} },
77  {3, 0x68, {0xB8, 0x56, 0x00, 0x00, 0x00, 0x00} },
78  {3, 0x68, {0xB8, 0x7E, 0x00, 0x00, 0x00, 0x00} },
79  {3, 0x68, {0xBB, 0x90, 0x10, 0x00, 0x00, 0x00} },
80  {3, 0x68, {0xBB, 0x91, 0x0F, 0x00, 0x00, 0x00} },
81  {3, 0x68, {0xBB, 0x92, 0xF6, 0x00, 0x00, 0x00} },
82  {3, 0x68, {0xBB, 0x93, 0x10, 0x00, 0x00, 0x00} },
83  {3, 0x68, {0xBB, 0x94, 0x0F, 0x00, 0x00, 0x00} },
84  {3, 0x68, {0xBB, 0x95, 0xF6, 0x00, 0x00, 0x00} },
85  {3, 0x68, {0xBB, 0x96, 0x10, 0x00, 0x00, 0x00} },
86  {3, 0x68, {0xBB, 0x97, 0x0F, 0x00, 0x00, 0x00} },
87  {3, 0x68, {0xBB, 0x98, 0xF6, 0x00, 0x00, 0x00} },
88  {3, 0x68, {0xBB, 0x99, 0x10, 0x00, 0x00, 0x00} },
89  {3, 0x68, {0xBB, 0x9A, 0x0F, 0x00, 0x00, 0x00} },
90  {3, 0x68, {0xBB, 0x9B, 0xF6, 0x00, 0x00, 0x00} },
91  {3, 0x68, {0xB8, 0x8A, 0x03, 0x00, 0x00, 0x00} },
92  {3, 0x68, {0xB8, 0x96, 0x03, 0x00, 0x00, 0x00} },
93  {3, 0x68, {0xBB, 0xD1, 0x07, 0x00, 0x00, 0x00} },
94  {3, 0x68, {0xBB, 0xB0, 0x07, 0x00, 0x00, 0x00} },
95  {3, 0x68, {0xB8, 0x8B, 0x04, 0x00, 0x00, 0x00} },
96  {3, 0x68, {0xB8, 0x8C, 0x45, 0x00, 0x00, 0x00} },
97  {3, 0x68, {0xB8, 0x8D, 0x05, 0x00, 0x00, 0x00} },
98  {3, 0x68, {0xB8, 0x97, 0x04, 0x00, 0x00, 0x00} },
99  {3, 0x68, {0xB8, 0x98, 0xE0, 0x00, 0x00, 0x00} },
100  {3, 0x68, {0xB8, 0x99, 0x2E, 0x00, 0x00, 0x00} },
101  {3, 0x68, {0x80, 0x0E, 0x00, 0x00, 0x00, 0x00} },
102  {6, 0x68, {0x10, 0x14, 0x07, 0x00, 0x00, 0x00} },
103  {6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF} },
104  /* Video size */
105  {6, 0x68, {0x01, 0x48, 0xB0, 0x04, 0x00, 0x00} },
106  {6, 0x68, {0x29, 0x20, 0x10, 0x0E, 0x0B, 0x3E} },
107  /* eDP */
108  {3, 0x68, {0xB6, 0x31, 0xFF, 0x00, 0x00, 0x00} },
109  {3, 0x68, {0x80, 0x01, 0x14, 0x00, 0x00, 0x00} },
110  {3, 0x68, {0x80, 0x02, 0x02, 0x00, 0x00, 0x00} },
111  {3, 0x68, {0xB6, 0x08, 0x0B, 0x00, 0x00, 0x00} },
112  {3, 0x68, {0xB8, 0x00, 0x1E, 0x00, 0x00, 0x00} },
113  {3, 0x68, {0x87, 0x00, 0x00, 0x00, 0x00, 0x00} },
114  {6, 0x68, {0x50, 0x10, 0x00, 0x00, 0x9D, 0x00} },
115  {6, 0x68, {0x00, 0x8C, 0x40, 0x00, 0x00, 0x00} },
116  {6, 0x68, {0x00, 0x80, 0x02, 0x00, 0x00, 0x00} },
117  /* Link Training */
118  {3, 0x68, {0x82, 0x02, 0xFF, 0x00, 0x00, 0x00} },
119  {3, 0x68, {0x82, 0x03, 0xFF, 0x00, 0x00, 0x00} },
120  {3, 0x68, {0x82, 0x04, 0xFF, 0x00, 0x00, 0x00} },
121  {6, 0x68, {0x21, 0x58, 0x09, 0x00, 0x28, 0x00} },
122  {6, 0x68, {0x21, 0x60, 0x07, 0x00, 0x0F, 0x00} },
123  {6, 0x68, {0x21, 0x64, 0x28, 0x23, 0x00, 0x00} },
124  {6, 0x68, {0x21, 0x68, 0x0E, 0x00, 0x00, 0x00} },
125  /* DSI */
126  {6, 0x68, {0x20, 0x7C, 0x81, 0x00, 0x00, 0x00} },
127  {6, 0x68, {0x20, 0x50, 0x00, 0x00, 0x00, 0x00} },
128  {6, 0x68, {0x20, 0x1C, 0x01, 0x00, 0x00, 0x00} },
129  {6, 0x68, {0x20, 0x60, 0xFF, 0xFF, 0xFF, 0xFF} },
130  /* GPIO */
131  {6, 0x68, {0x08, 0x04, 0x00, 0x00, 0x00, 0x00} },
132  {6, 0x68, {0x00, 0x80, 0x0F, 0x00, 0x00, 0x00} },
133  {6, 0x68, {0x00, 0x84, 0x0F, 0x00, 0x00, 0x00} },
134  {6, 0x68, {0x00, 0x84, 0x00, 0x00, 0x00, 0x00} },
135  {6, 0x68, {0x00, 0x84, 0x0F, 0x00, 0x00, 0x00} },
136  /* DSI clock */
137  {6, 0x68, {0x20, 0x50, 0x20, 0x00, 0x00, 0x00} },
138  /* LCD init */
139  {6, 0x68, {0x22, 0xFC, 0x15, 0x01, 0x00, 0x81} },
140  {6, 0x68, {0x22, 0xFC, 0x15, 0x8C, 0x80, 0x81} },
141  {6, 0x68, {0x22, 0xFC, 0x15, 0xC7, 0x50, 0x81} },
142  {6, 0x68, {0x22, 0xFC, 0x15, 0xC5, 0x50, 0x81} },
143  {6, 0x68, {0x22, 0xFC, 0x15, 0x85, 0x04, 0x81} },
144  {6, 0x68, {0x22, 0xFC, 0x15, 0x86, 0x08, 0x81} },
145  {6, 0x68, {0x22, 0xFC, 0x15, 0x83, 0xAA, 0x81} },
146  {6, 0x68, {0x22, 0xFC, 0x15, 0x84, 0x11, 0x81} },
147  {6, 0x68, {0x22, 0xFC, 0x15, 0x9C, 0x10, 0x81} },
148  {6, 0x68, {0x22, 0xFC, 0x15, 0xA9, 0x4B, 0x81} },
149  {6, 0x68, {0x22, 0xFC, 0x05, 0x11, 0x00, 0x81} },
150  {6, 0x68, {0x22, 0xFC, 0x05, 0x29, 0x00, 0x81} },
151  {6, 0x68, {0x2A, 0x10, 0x10, 0x00, 0x04, 0x80} },
152  {6, 0x68, {0x2A, 0x04, 0x01, 0x00, 0x00, 0x00} },
153  /* Check Video */
154  {6, 0x68, {0x01, 0x54, 0x01, 0x00, 0x00, 0x00} },
155  /* End of table */
156  {0, 0x00, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00} },
157 };
158 
159 static const struct edp_data b101uan08_table[] = {
160  /* set eDP bridge to 1200x1920 */
161  /* IO Voltage Setting */
162  {6, 0x68, {0x08, 0x00, 0x01, 0x00, 0x00, 0x00} },
163  /* Boot Settings */
164  {6, 0x68, {0x10, 0x00, 0x78, 0x69, 0x00, 0x00} },
165  {6, 0x68, {0x10, 0x04, 0x02, 0x08, 0x02, 0x00} },
166  {6, 0x68, {0x10, 0x08, 0x22, 0x00, 0xA0, 0x02} },
167  {6, 0x68, {0x10, 0x0C, 0x50, 0x04, 0x00, 0x03} },
168  {6, 0x68, {0x10, 0x10, 0x10, 0x0D, 0x06, 0x01} },
169  {6, 0x68, {0x10, 0x14, 0x01, 0x00, 0x00, 0x00} },
170  {6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF} },
171  /* Internal PCLK settings for Non Present or REFCLK=26MHz */
172  {3, 0x68, {0xB0, 0x05, 0x0A, 0x00, 0x00, 0x00} },
173  {3, 0x68, {0xB0, 0x06, 0x03, 0x00, 0x00, 0x00} },
174  {3, 0x68, {0xB0, 0x07, 0x16, 0x00, 0x00, 0x00} },
175  {3, 0x68, {0xB0, 0x08, 0x00, 0x00, 0x00, 0x00} },
176  {3, 0x68, {0xB0, 0x09, 0x21, 0x00, 0x00, 0x00} },
177  {3, 0x68, {0xB0, 0x0A, 0x07, 0x00, 0x00, 0x00} },
178  /* DSI Clock setting for Non Preset or REFCLK=26MHz */
179  {6, 0x68, {0x41, 0xB0, 0xC1, 0x22, 0x04, 0x00} },
180  {6, 0x68, {0x41, 0xBC, 0x01, 0x0E, 0x00, 0x00} },
181  {6, 0x68, {0x41, 0xC0, 0x30, 0x00, 0x00, 0x00} },
182  {6, 0x68, {0x10, 0x14, 0x03, 0x00, 0x00, 0x00} },
183  {6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF} },
184  /* Additional Setting for eDP */
185  {3, 0x68, {0x80, 0x03, 0x41, 0x00, 0x00, 0x00} },
186  {3, 0x68, {0xB4, 0x00, 0x0D, 0x00, 0x00, 0x00} },
187  /* DPRX CAD Register Setting */
188  {3, 0x68, {0xB8, 0x8E, 0xFF, 0x00, 0x00, 0x00} },
189  {3, 0x68, {0xB8, 0x8F, 0xFF, 0x00, 0x00, 0x00} },
190  {3, 0x68, {0xB8, 0x9A, 0xFF, 0x00, 0x00, 0x00} },
191  {3, 0x68, {0xB8, 0x9B, 0xFF, 0x00, 0x00, 0x00} },
192  {3, 0x68, {0xB8, 0x00, 0x0E, 0x00, 0x00, 0x00} },
193  {3, 0x68, {0xBB, 0x26, 0x02, 0x00, 0x00, 0x00} },
194  {3, 0x68, {0xBB, 0x01, 0x20, 0x00, 0x00, 0x00} },
195  {3, 0x68, {0xB8, 0xC0, 0xF1, 0x00, 0x00, 0x00} },
196  {3, 0x68, {0xB8, 0xC1, 0xF1, 0x00, 0x00, 0x00} },
197  {3, 0x68, {0xB8, 0xC2, 0xF0, 0x00, 0x00, 0x00} },
198  {3, 0x68, {0xB8, 0xC3, 0xF0, 0x00, 0x00, 0x00} },
199  {3, 0x68, {0xB8, 0xC4, 0xF0, 0x00, 0x00, 0x00} },
200  {3, 0x68, {0xB8, 0xC5, 0xF0, 0x00, 0x00, 0x00} },
201  {3, 0x68, {0xB8, 0xC6, 0xF0, 0x00, 0x00, 0x00} },
202  {3, 0x68, {0xB8, 0xC7, 0xF0, 0x00, 0x00, 0x00} },
203  {3, 0x68, {0xB8, 0x0B, 0x00, 0x00, 0x00, 0x00} },
204  {3, 0x68, {0xB8, 0x33, 0x00, 0x00, 0x00, 0x00} },
205  {3, 0x68, {0xB8, 0x5B, 0x00, 0x00, 0x00, 0x00} },
206  {3, 0x68, {0xB8, 0x10, 0x00, 0x00, 0x00, 0x00} },
207  {3, 0x68, {0xB8, 0x38, 0x00, 0x00, 0x00, 0x00} },
208  {3, 0x68, {0xB8, 0x60, 0x00, 0x00, 0x00, 0x00} },
209  {3, 0x68, {0xB8, 0x15, 0x00, 0x00, 0x00, 0x00} },
210  {3, 0x68, {0xB8, 0x3D, 0x00, 0x00, 0x00, 0x00} },
211  {3, 0x68, {0xB8, 0x65, 0x00, 0x00, 0x00, 0x00} },
212  {3, 0x68, {0xB8, 0x1A, 0x00, 0x00, 0x00, 0x00} },
213  {3, 0x68, {0xB8, 0x42, 0x00, 0x00, 0x00, 0x00} },
214  {3, 0x68, {0xB8, 0x6A, 0x00, 0x00, 0x00, 0x00} },
215  {3, 0x68, {0xB8, 0x1F, 0x00, 0x00, 0x00, 0x00} },
216  {3, 0x68, {0xB8, 0x47, 0x00, 0x00, 0x00, 0x00} },
217  {3, 0x68, {0xB8, 0x6F, 0x00, 0x00, 0x00, 0x00} },
218  {3, 0x68, {0xB8, 0x24, 0x00, 0x00, 0x00, 0x00} },
219  {3, 0x68, {0xB8, 0x4C, 0x00, 0x00, 0x00, 0x00} },
220  {3, 0x68, {0xB8, 0x74, 0x00, 0x00, 0x00, 0x00} },
221  {3, 0x68, {0xB8, 0x29, 0x00, 0x00, 0x00, 0x00} },
222  {3, 0x68, {0xB8, 0x51, 0x00, 0x00, 0x00, 0x00} },
223  {3, 0x68, {0xB8, 0x79, 0x00, 0x00, 0x00, 0x00} },
224  {3, 0x68, {0xB8, 0x2E, 0x00, 0x00, 0x00, 0x00} },
225  {3, 0x68, {0xB8, 0x56, 0x00, 0x00, 0x00, 0x00} },
226  {3, 0x68, {0xB8, 0x7E, 0x00, 0x00, 0x00, 0x00} },
227  {3, 0x68, {0xBB, 0x90, 0x10, 0x00, 0x00, 0x00} },
228  {3, 0x68, {0xBB, 0x91, 0x0F, 0x00, 0x00, 0x00} },
229  {3, 0x68, {0xBB, 0x92, 0xF6, 0x00, 0x00, 0x00} },
230  {3, 0x68, {0xBB, 0x93, 0x10, 0x00, 0x00, 0x00} },
231  {3, 0x68, {0xBB, 0x94, 0x0F, 0x00, 0x00, 0x00} },
232  {3, 0x68, {0xBB, 0x95, 0xF6, 0x00, 0x00, 0x00} },
233  {3, 0x68, {0xBB, 0x96, 0x10, 0x00, 0x00, 0x00} },
234  {3, 0x68, {0xBB, 0x97, 0x0F, 0x00, 0x00, 0x00} },
235  {3, 0x68, {0xBB, 0x98, 0xF6, 0x00, 0x00, 0x00} },
236  {3, 0x68, {0xBB, 0x99, 0x10, 0x00, 0x00, 0x00} },
237  {3, 0x68, {0xBB, 0x9A, 0x0F, 0x00, 0x00, 0x00} },
238  {3, 0x68, {0xBB, 0x9B, 0xF6, 0x00, 0x00, 0x00} },
239  {3, 0x68, {0xB8, 0x8A, 0x03, 0x00, 0x00, 0x00} },
240  {3, 0x68, {0xB8, 0x96, 0x03, 0x00, 0x00, 0x00} },
241  {3, 0x68, {0xBB, 0xD1, 0x07, 0x00, 0x00, 0x00} },
242  {3, 0x68, {0xBB, 0xB0, 0x07, 0x00, 0x00, 0x00} },
243  {3, 0x68, {0xB8, 0x8B, 0x04, 0x00, 0x00, 0x00} },
244  {3, 0x68, {0xB8, 0x8C, 0x45, 0x00, 0x00, 0x00} },
245  {3, 0x68, {0xB8, 0x8D, 0x05, 0x00, 0x00, 0x00} },
246  {3, 0x68, {0xB8, 0x97, 0x04, 0x00, 0x00, 0x00} },
247  {3, 0x68, {0xB8, 0x98, 0xE0, 0x00, 0x00, 0x00} },
248  {3, 0x68, {0xB8, 0x99, 0x2E, 0x00, 0x00, 0x00} },
249  {3, 0x68, {0x80, 0x0E, 0x00, 0x00, 0x00, 0x00} },
250  {6, 0x68, {0x10, 0x14, 0x07, 0x00, 0x00, 0x00} },
251  {6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF} },
252  /* Video size Related Settings for Non Present */
253  {6, 0x68, {0x01, 0x48, 0xB0, 0x04, 0x00, 0x00} },
254  {6, 0x68, {0x29, 0x20, 0x10, 0x0E, 0x0B, 0x3E} },
255  /* eDP Settings for Link Training*/
256  {3, 0x68, {0xB6, 0x31, 0xFF, 0x00, 0x00, 0x00} },
257  {3, 0x68, {0x80, 0x01, 0x14, 0x00, 0x00, 0x00} },
258  {3, 0x68, {0x80, 0x02, 0x02, 0x00, 0x00, 0x00} },
259  {3, 0x68, {0xB6, 0x08, 0x0B, 0x00, 0x00, 0x00} },
260  {3, 0x68, {0xB8, 0x00, 0x1E, 0x00, 0x00, 0x00} },
261  {3, 0x68, {0x87, 0x00, 0x00, 0x00, 0x00, 0x00} },
262  {6, 0x68, {0x50, 0x10, 0x00, 0x00, 0x9D, 0x00} },
263  {6, 0x68, {0x00, 0x8C, 0x40, 0x00, 0x00, 0x00} },
264  {6, 0x68, {0x00, 0x80, 0x02, 0x00, 0x00, 0x00} },
265  /* Link Training */
266  {3, 0x68, {0x82, 0x02, 0xFF, 0x00, 0x00, 0x00} },
267  {3, 0x68, {0x82, 0x03, 0xFF, 0x00, 0x00, 0x00} },
268  {3, 0x68, {0x82, 0x04, 0xFF, 0x00, 0x00, 0x00} },
269  /* DSI Transition Time Setting for Non Preset */
270  {6, 0x68, {0x21, 0x54, 0x0D, 0x00, 0x00, 0x00} },
271  {6, 0x68, {0x21, 0x58, 0x06, 0x00, 0x2A, 0x00} },
272  {6, 0x68, {0x21, 0x5C, 0x07, 0x00, 0x0E, 0x00} },
273  {6, 0x68, {0x21, 0x60, 0x07, 0x00, 0x10, 0x00} },
274  {6, 0x68, {0x21, 0x64, 0x10, 0x27, 0x00, 0x00} },
275  {6, 0x68, {0x21, 0x68, 0x0E, 0x00, 0x00, 0x00} },
276  {6, 0x68, {0x21, 0x6C, 0x0A, 0x00, 0x0E, 0x00} },
277  {6, 0x68, {0x21, 0x78, 0x0E, 0x00, 0x0D, 0x00} },
278  /* DSI Start */
279  {6, 0x68, {0x20, 0x7C, 0x81, 0x00, 0x00, 0x00} },
280  {6, 0x68, {0x20, 0x50, 0x00, 0x00, 0x00, 0x00} },
281  {6, 0x68, {0x20, 0x1C, 0x01, 0x00, 0x00, 0x00} },
282  {6, 0x68, {0x20, 0x60, 0xFF, 0xFF, 0xFF, 0xFF} },
283  /* GPIO for LCD control*/
284  {6, 0x68, {0x08, 0x04, 0x00, 0x00, 0x00, 0x00} },
285  {6, 0x68, {0x00, 0x80, 0x0F, 0x00, 0x00, 0x00} },
286  {6, 0x68, {0x00, 0x84, 0x0F, 0x00, 0x00, 0x00} },
287  {6, 0x68, {0x00, 0x84, 0x00, 0x00, 0x00, 0x00} },
288  {6, 0x68, {0x00, 0x84, 0x0F, 0x00, 0x00, 0x00} },
289  /* DSI Hs Clock Mode */
290  {6, 0x68, {0x20, 0x50, 0x20, 0x00, 0x00, 0x00} },
291  /* LCD Initialization */
292  {6, 0x68, {0x22, 0xFC, 0x15, 0xBF, 0xA5, 0x81} },
293  {6, 0x68, {0x22, 0xFC, 0x15, 0x01, 0x00, 0x81} },
294  {6, 0x68, {0x22, 0xFC, 0x15, 0x8F, 0xA5, 0x81} },
295  {6, 0x68, {0x22, 0xFC, 0x15, 0x83, 0xAA, 0x81} },
296  {6, 0x68, {0x22, 0xFC, 0x15, 0x84, 0x11, 0x81} },
297  {6, 0x68, {0x22, 0xFC, 0x15, 0xA9, 0x48, 0x81} },
298  {6, 0x68, {0x22, 0xFC, 0x15, 0x83, 0x00, 0x81} },
299  {6, 0x68, {0x22, 0xFC, 0x15, 0x84, 0x00, 0x81} },
300  {6, 0x68, {0x22, 0xFC, 0x15, 0x8F, 0x00, 0x81} },
301  {6, 0x68, {0x2A, 0x10, 0x10, 0x00, 0x04, 0x80} },
302  {6, 0x68, {0x2A, 0x04, 0x01, 0x00, 0x00, 0x00} },
303  /* Check if eDP video is coming */
304  {6, 0x68, {0x01, 0x54, 0x01, 0x00, 0x00, 0x00} },
305  /* End of table */
306  {0, 0x00, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00} },
307 };
308 
309 static void mainboard_configure_edp_bridge(void)
310 {
311  const struct edp_data *edptable;
312  unsigned int loops;
313  unsigned int pcb_version;
314  int status;
315 
316  pcb_version = cpld_read_pcb_version();
317  printk(BIOS_DEBUG, "PCB version: %x\n", pcb_version);
318 
319  if (pcb_version < 7)
320  edptable = b101uan01_table;
321  else
322  edptable = b101uan08_table;
323 
324  /* reset bridge */
325  cpld_reset_bridge();
326 
327  while (edptable->payload_length) {
328  loops = 5;
329  do {
330  status = smbus_i2c_block_write(edptable->address,
331  edptable->payload_length,
332  (u8 *)&edptable->data[0]);
333  } while (--loops && (status < 0));
334 
335  if (loops == 0) {
336  printk(BIOS_ERR, "Writing eDP bridge failed!\n");
337  return;
338  }
339  edptable++;
340  };
341 }
342 
343 void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
344 {
345  mainboard_configure_edp_bridge();
346 }
params
static struct sdram_info params
Definition: sdram_configs.c:83
printk
#define printk(level,...)
Definition: stdlib.h:16
cpld_reset_bridge
void cpld_reset_bridge(void)
Definition: cpld.c:16
cpld_read_pcb_version
unsigned int cpld_read_pcb_version(void)
Definition: cpld.c:23
mainboard_silicon_init_params
__weak void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
Definition: ramstage.c:162
BIOS_DEBUG
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
Definition: loglevel.h:128
BIOS_ERR
#define BIOS_ERR
BIOS_ERR - System in incomplete state.
Definition: loglevel.h:72
__packed
struct edp_data __packed
mainboard_configure_edp_bridge
static void mainboard_configure_edp_bridge(void)
Definition: ramstage.c:309
b101uan01_table
static const struct edp_data b101uan01_table[]
Definition: ramstage.c:15
b101uan08_table
static const struct edp_data b101uan08_table[]
Definition: ramstage.c:159
smbus_i2c_block_write
int smbus_i2c_block_write(u8 addr, u8 bytes, u8 *buf)
Definition: smbus.c:13
u8
uint8_t u8
Definition: stdint.h:45
edp_data
Definition: ramstage.c:8
edp_data::address
u8 address
Definition: ramstage.c:10
edp_data::payload_length
u8 payload_length
Definition: ramstage.c:9
edp_data::data
u8 data[6]
Definition: ramstage.c:12