coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
smbus.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #define __SIMPLE_DEVICE__
4 
5 #include <soc/iomap.h>
6 #include <soc/pci_devs.h>
7 #include <device/pci_def.h>
8 #include <device/pci_type.h>
9 #include <device/pci_ops.h>
10 #include <device/smbus_host.h>
11 #include <soc/smbus.h>
12 
14 {
15  const pci_devfn_t dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);
16 
17  u32 smbase;
18  u32 smb_ctrl_reg;
19  int status;
20 
21  /* SMBus I/O BAR */
22  smbase = pci_read_config32(dev, PCI_BASE_ADDRESS_4) & 0xFFFFFFFE;
23 
24  /* Enable I2C_EN bit in HOSTC register */
25  smb_ctrl_reg = pci_read_config32(dev, HOSTC);
26  pci_write_config32(dev, HOSTC, smb_ctrl_reg | HOSTC_I2C_EN);
27 
28  status = do_i2c_block_write(smbase, addr, bytes, buf);
29 
30  /* Restore I2C_EN bit */
31  pci_write_config32(dev, HOSTC, smb_ctrl_reg);
32 
33  return status;
34 }
static u32 addr
Definition: cirrus.c:14
static __always_inline void pci_write_config32(const struct device *dev, u16 reg, u32 val)
Definition: pci_ops.h:76
static __always_inline u32 pci_read_config32(const struct device *dev, u16 reg)
Definition: pci_ops.h:58
static uint8_t * buf
Definition: uart.c:7
#define PCI_BASE_ADDRESS_4
Definition: pci_def.h:67
#define PCI_DEV(SEGBUS, DEV, FN)
Definition: pci_type.h:14
u32 pci_devfn_t
Definition: pci_type.h:8
#define SMBUS_DEV
Definition: pci_devs.h:115
#define SMBUS_FUNC
Definition: pci_devs.h:116
#define HOSTC_I2C_EN
Definition: smbus.h:8
#define HOSTC
Definition: smbus.h:7
int smbus_i2c_block_write(u8 addr, u8 bytes, u8 *buf)
Definition: smbus.c:13
int do_i2c_block_write(uintptr_t base, u8 device, size_t bytes, u8 *buf)
Definition: smbus.c:503
uint32_t u32
Definition: stdint.h:51
uint8_t u8
Definition: stdint.h:45