#include <assert.h>
#include <device/mmio.h>
#include <console/console.h>
#include <delay.h>
#include <soc/dsi.h>
#include <timer.h>

Include dependency graph for dsi.c:

Functions
void	mtk_dsi_configure_mipi_tx (u32 data_rate, u32 lanes)

void	mtk_dsi_reset (void)

void	mtk_dsi_override_phy_timing (struct mtk_phy_timing *timing)

void	mtk_dsi_pin_drv_ctrl (void)

Function Documentation

◆ mtk_dsi_configure_mipi_tx()

void mtk_dsi_configure_mipi_tx	(	u32	data_rate,
		u32	lanes
	)

PLL PCW config PCW bit 24~30 = integer part of pcw PCW bit 0~23 = fractional part of pcw pcw = data_Rate*4*txdiv/(Ref_clk*2); Post DIV =4, so need data_Rate*4 Ref_clk is 26MHz

Definition at line 10 of file dsi.c.

References AD_DSI_PLL_SDM_ISO_EN, AD_DSI_PLL_SDM_PWR_ON, assert, BIT, mipi_tx_regs::ck_ckmode_en, mipi_tx_regs::ck_sw_ctl_en, CLK26M_HZ, clrbits32, clrsetbits32, mipi_tx_regs::d0_sw_ctl_en, mipi_tx_regs::d1_sw_ctl_en, mipi_tx_regs::d2_sw_ctl_en, mipi_tx_regs::d3_sw_ctl_en, mipi_tx_regs::dsi_bg_con, DSI_CK_CKMODE_EN, mipi_tx_regs::dsi_clock_lane, mipi_tx_regs::dsi_con, mipi_tx_regs::dsi_data_lane, mipi_tx_regs::dsi_pll_con0, mipi_tx_regs::dsi_pll_con1, mipi_tx_regs::dsi_pll_con2, mipi_tx_regs::dsi_pll_pwr, DSI_SW_CTL_EN, mipi_tx_regs::dsi_top_con, mipi_tx_regs::lane_con, LDOOUT_EN, MHz, mipi_tx, mipi_tx0, MTK_DSI_DATA_RATE_MIN_MHZ, mipi_tx_regs::pll_con0, mipi_tx_regs::pll_con1, mipi_tx_regs::pll_con4, mipi_tx_regs::pll_pwr, read32(), RG_DSI0_CKG_LDOOUT_EN, RG_DSI0_LDOCORE_EN, RG_DSI0_MPPLL_PLL_EN, RG_DSI0_MPPLL_PREDIV, RG_DSI0_MPPLL_SDM_FRA_EN, RG_DSI0_MPPLL_SDM_SSC_EN, RG_DSI0_MPPLL_TXDIV0, RG_DSI0_MPPLL_TXDIV1, RG_DSI_BG_CKEN, RG_DSI_BG_CORE_EN, RG_DSI_LNT_HS_BIAS_EN, RG_DSI_LNT_IMP_CAL_CODE, RG_DSI_MPPLL_SDM_ISO_EN, RG_DSI_MPPLL_SDM_PWR_ON, RG_DSI_PAD_TIE_LOW_EN, RG_DSI_PLL_EN, RG_DSI_PLL_POSDIV, RG_DSI_V02_SEL, RG_DSI_V032_SEL, RG_DSI_V04_SEL, RG_DSI_V072_SEL, RG_DSI_V10_SEL, RG_DSI_V12_SEL, setbits32, udelay(), and write32().