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dsi.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef SOC_MEDIATEK_MT8183_DSI_H
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#define SOC_MEDIATEK_MT8183_DSI_H
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#include <
soc/dsi_common.h
>
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#include <types.h>
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/* DSI features */
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#define MTK_DSI_MIPI_RATIO_NUMERATOR 100
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#define MTK_DSI_MIPI_RATIO_DENOMINATOR 100
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#define MTK_DSI_DATA_RATE_MIN_MHZ 125
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#define MTK_DSI_HAVE_SIZE_CON 1
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#define PIXEL_STREAM_CUSTOM_HEADER 0xb
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/* MIPITX is SOC specific and cannot live in common. */
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/* MIPITX_REG */
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struct
mipi_tx_regs
{
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u32
reserved0
[3];
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u32
lane_con
;
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u32
reserved1
[6];
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u32
pll_pwr
;
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u32
pll_con0
;
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u32
pll_con1
;
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u32
pll_con2
;
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u32
pll_con3
;
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u32
pll_con4
;
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u32
reserved2
[65];
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u32
d2_sw_ctl_en
;
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u32
reserved3
[63];
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u32
d0_sw_ctl_en
;
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u32
reserved4
[56];
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u32
ck_ckmode_en
;
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u32
reserved5
[6];
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u32
ck_sw_ctl_en
;
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u32
reserved6
[63];
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u32
d1_sw_ctl_en
;
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u32
reserved7
[63];
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u32
d3_sw_ctl_en
;
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};
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check_member
(
mipi_tx_regs
, pll_con4, 0x3c);
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check_member
(
mipi_tx_regs
, d3_sw_ctl_en, 0x544);
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static
struct
mipi_tx_regs
*
const
mipi_tx
= (
void
*)
MIPITX_BASE
;
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/* Register values */
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#define DSI_CK_CKMODE_EN BIT(0)
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#define DSI_SW_CTL_EN BIT(0)
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#define AD_DSI_PLL_SDM_PWR_ON BIT(0)
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#define AD_DSI_PLL_SDM_ISO_EN BIT(1)
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#define RG_DSI_PLL_EN BIT(4)
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#define RG_DSI_PLL_POSDIV (0x7 << 8)
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#endif
dsi_common.h
check_member
check_member(mipi_tx_regs, dsi_top_con, 0x40)
MIPITX_BASE
@ MIPITX_BASE
Definition:
addressmap.h:41
mipi_tx
static struct mipi_tx_regs *const mipi_tx
Definition:
dsi.h:45
u32
uint32_t u32
Definition:
stdint.h:51
mipi_tx_regs
Definition:
dsi.h:19
mipi_tx_regs::d0_sw_ctl_en
u32 d0_sw_ctl_en
Definition:
dsi.h:32
mipi_tx_regs::reserved0
u8 reserved0[40]
Definition:
dsi.h:23
mipi_tx_regs::d2_sw_ctl_en
u32 d2_sw_ctl_en
Definition:
dsi.h:30
mipi_tx_regs::ck_sw_ctl_en
u32 ck_sw_ctl_en
Definition:
dsi.h:36
mipi_tx_regs::ck_ckmode_en
u32 ck_ckmode_en
Definition:
dsi.h:34
mipi_tx_regs::pll_con2
u32 pll_con2
Definition:
dsi.h:26
mipi_tx_regs::d1_sw_ctl_en
u32 d1_sw_ctl_en
Definition:
dsi.h:38
mipi_tx_regs::reserved3
u32 reserved3[63]
Definition:
dsi.h:31
mipi_tx_regs::reserved4
u32 reserved4[56]
Definition:
dsi.h:33
mipi_tx_regs::lane_con
u32 lane_con
Definition:
dsi.h:21
mipi_tx_regs::pll_pwr
u32 pll_pwr
Definition:
dsi.h:23
mipi_tx_regs::pll_con3
u32 pll_con3
Definition:
dsi.h:27
mipi_tx_regs::reserved1
u8 reserved1[8]
Definition:
dsi.h:26
mipi_tx_regs::pll_con4
u32 pll_con4
Definition:
dsi.h:28
mipi_tx_regs::pll_con1
u32 pll_con1
Definition:
dsi.h:25
mipi_tx_regs::reserved7
u32 reserved7[63]
Definition:
dsi.h:39
mipi_tx_regs::pll_con0
u32 pll_con0
Definition:
dsi.h:24
mipi_tx_regs::reserved2
u8 reserved2[4]
Definition:
dsi.h:34
mipi_tx_regs::reserved5
u32 reserved5[6]
Definition:
dsi.h:35
mipi_tx_regs::reserved6
u32 reserved6[63]
Definition:
dsi.h:37
mipi_tx_regs::d3_sw_ctl_en
u32 d3_sw_ctl_en
Definition:
dsi.h:40
src
soc
mediatek
mt8183
include
soc
dsi.h
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