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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <chip.h>
Public Types | |
| enum | { SaGv_Disabled , SaGv_FixedPoint0 , SaGv_FixedPoint1 , SaGv_FixedPoint2 , SaGv_Enabled } |
| enum | { DEBUG_INTERFACE_RAM = (1 << 0) , DEBUG_INTERFACE_UART_8250IO = (1 << 1) , DEBUG_INTERFACE_USB3 = (1 << 3) , DEBUG_INTERFACE_LPSS_SERIAL_IO = (1 << 4) , DEBUG_INTERFACE_TRACEHUB = (1 << 5) } |
| anonymous enum |
| anonymous enum |
| struct soc_intel_common_config soc_intel_elkhartlake_config::common_soc_config |
| enum { ... } soc_intel_elkhartlake_config::debug_interface_flag |
| struct { ... } soc_intel_elkhartlake_config::fivr |
| uint8_t soc_intel_elkhartlake_config::gpio_pm[TOTAL_GPIO_COMM] |
| struct ehl_ibecc_config soc_intel_elkhartlake_config::ibecc |
| bool soc_intel_elkhartlake_config::MemoryThermalThrottlingDisable |
| uint8_t soc_intel_elkhartlake_config::PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS] |
| uint8_t soc_intel_elkhartlake_config::PchHdaAudioLinkHdaEnable |
| uint8_t soc_intel_elkhartlake_config::PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS] |
| uint8_t soc_intel_elkhartlake_config::PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS] |
| uint8_t soc_intel_elkhartlake_config::PchHdaSdiEnable[MAX_HD_AUDIO_SDI_LINKS] |
| enum tsn_gbe_link_speed soc_intel_elkhartlake_config::PchTsnGbeLinkSpeed |
| uint8_t soc_intel_elkhartlake_config::PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_SRC] |
| uint8_t soc_intel_elkhartlake_config::PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCK_SRC] |
| uint8_t soc_intel_elkhartlake_config::PciePtm[CONFIG_MAX_ROOT_PORTS] |
| uint8_t soc_intel_elkhartlake_config::PcieRpAdvancedErrorReportingDisable[CONFIG_MAX_ROOT_PORTS] |
| uint8_t soc_intel_elkhartlake_config::PcieRpClkReqDetectDisable[CONFIG_MAX_ROOT_PORTS] |
| uint8_t soc_intel_elkhartlake_config::PcieRpEnable[CONFIG_MAX_ROOT_PORTS] |
| uint8_t soc_intel_elkhartlake_config::PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS] |
| enum L1_substates_control soc_intel_elkhartlake_config::PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS] |
| uint8_t soc_intel_elkhartlake_config::PcieRpLtrDisable[CONFIG_MAX_ROOT_PORTS] |
| struct soc_power_limits_config soc_intel_elkhartlake_config::power_limits_config |
| enum pse_device_ownership soc_intel_elkhartlake_config::PseAdcOwn |
| enum pse_device_ownership soc_intel_elkhartlake_config::PseCanOwn[2] |
| enum pse_device_ownership soc_intel_elkhartlake_config::PseDmaOwn[3] |
| enum pse_device_ownership soc_intel_elkhartlake_config::PseGbeOwn[MAX_PSE_TSN_PORTS] |
| enum pse_device_ownership soc_intel_elkhartlake_config::PseHsuartOwn[4] |
| enum pse_device_ownership soc_intel_elkhartlake_config::PseI2cOwn[8] |
| enum pse_device_ownership soc_intel_elkhartlake_config::PseI2sOwn[2] |
| enum pse_device_ownership soc_intel_elkhartlake_config::PsePwmOwn |
| enum pse_device_ownership soc_intel_elkhartlake_config::PseQepOwn[4] |
| enum pse_device_ownership soc_intel_elkhartlake_config::PseSpiCs0Own[4] |
| enum pse_device_ownership soc_intel_elkhartlake_config::PseSpiCs1Own[4] |
| enum pse_device_ownership soc_intel_elkhartlake_config::PseSpiOwn[4] |
| enum tsn_gbe_link_speed soc_intel_elkhartlake_config::PseTsnGbeLinkSpeed[MAX_PSE_TSN_PORTS] |
| bool soc_intel_elkhartlake_config::PseTsnGbeMultiVcEnable[MAX_PSE_TSN_PORTS] |
| enum tsn_phy_type soc_intel_elkhartlake_config::PseTsnGbePhyType[MAX_PSE_TSN_PORTS] |
| bool soc_intel_elkhartlake_config::PseTsnGbeSgmiiEnable[MAX_PSE_TSN_PORTS] |
| enum pse_device_ownership soc_intel_elkhartlake_config::PseUartOwn[6] |
| enum { ... } soc_intel_elkhartlake_config::SaGv |
| uint8_t soc_intel_elkhartlake_config::SataPortsDevSlp[CONFIG_MAX_SATA_PORTS] |
| uint16_t soc_intel_elkhartlake_config::SataPortsDitoVal[CONFIG_MAX_SATA_PORTS] |
| uint8_t soc_intel_elkhartlake_config::SataPortsDmVal[CONFIG_MAX_SATA_PORTS] |
| uint8_t soc_intel_elkhartlake_config::SataPortsEnable[CONFIG_MAX_SATA_PORTS] |
| uint8_t soc_intel_elkhartlake_config::SataPortsEnableDitoConfig[CONFIG_MAX_SATA_PORTS] |
| uint8_t soc_intel_elkhartlake_config::SdCardPowerEnableActiveHigh |
| uint8_t soc_intel_elkhartlake_config::SerialIoGSpiCsEnable[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX] |
| uint8_t soc_intel_elkhartlake_config::SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX] |
| uint8_t soc_intel_elkhartlake_config::SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX] |
| uint8_t soc_intel_elkhartlake_config::SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX] |
| uint8_t soc_intel_elkhartlake_config::SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX] |
| uint8_t soc_intel_elkhartlake_config::SerialIoI2cPadsTermination[CONFIG_SOC_INTEL_I2C_DEV_MAX] |
| uint8_t soc_intel_elkhartlake_config::SerialIoUartDmaEnable[CONFIG_SOC_INTEL_UART_DEV_MAX] |
| uint8_t soc_intel_elkhartlake_config::SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX] |
| uint8_t soc_intel_elkhartlake_config::SkipCpuReplacementCheck |
| struct usb2_port_config soc_intel_elkhartlake_config::usb2_ports[10] |
| uint16_t soc_intel_elkhartlake_config::usb2_wake_enable_bitmap |
| struct usb3_port_config soc_intel_elkhartlake_config::usb3_ports[4] |
| uint16_t soc_intel_elkhartlake_config::usb3_wake_enable_bitmap |
| enum fivr_supported_voltage soc_intel_elkhartlake_config::v1p05_rail |
| enum fivr_states soc_intel_elkhartlake_config::v1p05_state |
| enum fivr_supported_voltage soc_intel_elkhartlake_config::vnn_rail |
| enum fivr_states soc_intel_elkhartlake_config::vnn_state |
| enum fivr_states soc_intel_elkhartlake_config::vnn_sx_state |
1.9.1