coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
chip.h File Reference
#include <drivers/i2c/designware/dw_i2c.h>
#include <intelblocks/cfg.h>
#include <intelblocks/gpio.h>
#include <intelblocks/gspi.h>
#include <intelblocks/pcie_rp.h>
#include <intelblocks/power_limit.h>
#include <soc/gpe.h>
#include <soc/gpio.h>
#include <soc/gpio_defs.h>
#include <soc/pch.h>
#include <soc/pci_devs.h>
#include <soc/pmc.h>
#include <soc/serialio.h>
#include <soc/usb.h>
#include <stdint.h>
Include dependency graph for chip.h:
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Go to the source code of this file.

Data Structures

struct  ehl_ibecc_config
 
struct  soc_intel_elkhartlake_config
 

Macros

#define MAX_HD_AUDIO_SDI_LINKS   2
 
#define MAX_HD_AUDIO_DMIC_LINKS   2
 
#define MAX_HD_AUDIO_SNDW_LINKS   4
 
#define MAX_HD_AUDIO_SSP_LINKS   6
 
#define MAX_PSE_TSN_PORTS   2
 
#define MAX_IBECC_REGIONS   8
 

Typedefs

typedef struct soc_intel_elkhartlake_config config_t
 

Enumerations

enum  ibecc_mode { IBECC_PER_REGION , IBECC_NONE , IBECC_ALL }
 
enum  tsn_gbe_link_speed { Tsn_2_5_Gbps , Tsn_1_Gbps }
 
enum  tsn_phy_type { RGMII = 1 , SGMII = 2 , SGMII_plus = 3 }
 
enum  pse_device_ownership { Device_Disabled , PSE_Owned , Host_Owned }
 
enum  fivr_states {
  FIVR_ENABLE_S0i3 = BIT(1) , FIVR_ENABLE_S3 = BIT(2) , FIVR_ENABLE_S4 = BIT(3) , FIVR_ENABLE_S5 = BIT(4) ,
  FIVR_ENABLE_S3_S4_S5 = FIVR_ENABLE_S3 | FIVR_ENABLE_S4 | FIVR_ENABLE_S5 , FIVR_ENABLE_ALL_SX = FIVR_ENABLE_S0i3 | FIVR_ENABLE_S3_S4_S5
}
 
enum  fivr_supported_voltage { FIVR_VOLTAGE_NORMAL = BIT(1) , FIVR_VOLTAGE_MIN_ACTIVE = BIT(2) , FIVR_VOLTAGE_MIN_RETENTION = BIT(3) , FIVR_ENABLE_ALL_VOLTAGE }
 

Macro Definition Documentation

◆ MAX_HD_AUDIO_DMIC_LINKS

#define MAX_HD_AUDIO_DMIC_LINKS   2

Definition at line 23 of file chip.h.

◆ MAX_HD_AUDIO_SDI_LINKS

#define MAX_HD_AUDIO_SDI_LINKS   2

Definition at line 22 of file chip.h.

◆ MAX_HD_AUDIO_SNDW_LINKS

#define MAX_HD_AUDIO_SNDW_LINKS   4

Definition at line 24 of file chip.h.

◆ MAX_HD_AUDIO_SSP_LINKS

#define MAX_HD_AUDIO_SSP_LINKS   6

Definition at line 25 of file chip.h.

◆ MAX_IBECC_REGIONS

#define MAX_IBECC_REGIONS   8

Definition at line 29 of file chip.h.

◆ MAX_PSE_TSN_PORTS

#define MAX_PSE_TSN_PORTS   2

Definition at line 26 of file chip.h.

Typedef Documentation

◆ config_t

Definition at line 1 of file chip.h.

Enumeration Type Documentation

◆ fivr_states

Enumerator
FIVR_ENABLE_S0i3 
FIVR_ENABLE_S3 
FIVR_ENABLE_S4 
FIVR_ENABLE_S5 
FIVR_ENABLE_S3_S4_S5 
FIVR_ENABLE_ALL_SX 

Definition at line 77 of file chip.h.

◆ fivr_supported_voltage

Enumerator
FIVR_VOLTAGE_NORMAL 
FIVR_VOLTAGE_MIN_ACTIVE 
FIVR_VOLTAGE_MIN_RETENTION 
FIVR_ENABLE_ALL_VOLTAGE 

Definition at line 92 of file chip.h.

◆ ibecc_mode

enum ibecc_mode
Enumerator
IBECC_PER_REGION 
IBECC_NONE 
IBECC_ALL 

Definition at line 31 of file chip.h.

◆ pse_device_ownership

Enumerator
Device_Disabled 
PSE_Owned 
Host_Owned 

Definition at line 65 of file chip.h.

◆ tsn_gbe_link_speed

Enumerator
Tsn_2_5_Gbps 
Tsn_1_Gbps 

Definition at line 47 of file chip.h.

◆ tsn_phy_type

Enumerator
RGMII 
SGMII 
SGMII_plus 

Definition at line 53 of file chip.h.