coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
smihandler.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <cpu/x86/smm.h>
4 #include <device/pci_ops.h>
7 #include <ec/acpi/ec.h>
8 
9 void mainboard_smi_gpi(u32 gpi_sts)
10 {
11 }
12 
14 {
15  u8 tmp;
16  switch (data) {
18  tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
19  tmp &= ~0x03;
20  tmp |= 0x02;
21  pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
22  break;
24  tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
25  tmp &= ~0x03;
26  tmp |= 0x01;
27  pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
28  break;
29  default:
30  break;
31  }
32  return 0;
33 }
int __weak mainboard_smi_apmc(u8 data)
Definition: smihandler.c:209
void __weak mainboard_smi_gpi(u32 gpi_sts)
Definition: smihandler.c:208
#define APM_CNT_ACPI_DISABLE
Definition: smm.h:21
#define APM_CNT_ACPI_ENABLE
Definition: smm.h:22
static __always_inline u8 pci_read_config8(const struct device *dev, u16 reg)
Definition: pci_ops.h:46
static __always_inline void pci_write_config8(const struct device *dev, u16 reg, u8 val)
Definition: pci_ops.h:64
#define PCI_DEV(SEGBUS, DEV, FN)
Definition: pci_type.h:14
uint32_t u32
Definition: stdint.h:51
uint8_t u8
Definition: stdint.h:45