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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <cpu/x86/smm.h>
Go to the source code of this file.
Macros | |
#define | D31F0_PMBASE 0x40 |
#define | D31F0_GEN_PMCON_1 0xa0 |
#define | SMI_LOCK (1 << 4) |
#define | D31F0_GEN_PMCON_2 0xa2 |
#define | D31F0_GEN_PMCON_3 0xa4 |
#define | RTC_BATTERY_DEAD (1 << 2) |
#define | RTC_POWER_FAILED (1 << 1) |
#define | SLEEP_AFTER_POWER_FAIL (1 << 0) |
#define | D31F0_GEN_PMCON_LOCK 0xa6 |
#define | ACPI_BASE_LOCK (1 << 1) |
#define | SLP_STR_POL_LOCK (1 << 2) |
#define | D31F0_ETR3 0xac |
#define | ETR3_CWORWRE (1 << 18) |
#define | ETR3_CF9GR (1 << 20) |
#define | ETR3_CF9LOCK (1 << 31) |
#define | D31F0_GPIO_ROUT 0xb8 |
#define | GPI_DISABLE 0x00 |
#define | GPI_IS_SMI 0x01 |
#define | GPI_IS_SCI 0x02 |
#define | GPI_IS_NMI 0x03 |
#define | MAINBOARD_POWER_OFF 0 |
#define | MAINBOARD_POWER_ON 1 |
#define | MAINBOARD_POWER_KEEP 2 |
#define | PM1_STS 0x00 |
#define | WAK_STS (1 << 15) |
#define | PCIEXPWAK_STS (1 << 14) |
#define | PRBTNOR_STS (1 << 11) |
#define | RTC_STS (1 << 10) |
#define | PWRBTN_STS (1 << 8) |
#define | GBL_STS (1 << 5) |
#define | BM_STS (1 << 4) |
#define | TMROF_STS (1 << 0) |
#define | PM1_EN 0x02 |
#define | PCIEXPWAK_DIS (1 << 14) |
#define | RTC_EN (1 << 10) |
#define | PWRBTN_EN (1 << 8) |
#define | GBL_EN (1 << 5) |
#define | TMROF_EN (1 << 0) |
#define | PM1_CNT 0x04 |
#define | GBL_RLS (1 << 2) |
#define | BM_RLD (1 << 1) |
#define | SCI_EN (1 << 0) |
#define | PM1_TMR 0x08 |
#define | PROC_CNT 0x10 |
#define | LV2 0x14 |
#define | LV3 0x15 |
#define | LV4 0x16 |
#define | PM2_CNT 0x50 |
#define | GPE0_STS 0x20 |
#define | USB4_STS (1 << 14) /* i82801gx only */ |
#define | PME_B0_STS (1 << 13) |
#define | PME_STS (1 << 11) |
#define | BATLOW_STS (1 << 10) |
#define | PCI_EXP_STS (1 << 9) |
#define | RI_STS (1 << 8) |
#define | SMB_WAK_STS (1 << 7) |
#define | TCOSCI_STS (1 << 6) |
#define | SWGPE_STS (1 << 2) |
#define | HOT_PLUG_STS (1 << 1) |
#define | GPE0_EN 0x28 |
#define | PME_B0_EN (1 << 13) |
#define | PME_EN (1 << 11) |
#define | TCOSCI_EN (1 << 6) |
#define | SMI_EN 0x30 |
#define | INTEL_USB2_EN (1 << 18) |
#define | LEGACY_USB2_EN (1 << 17) |
#define | PERIODIC_EN (1 << 14) |
#define | TCO_EN (1 << 13) |
#define | MCSMI_EN (1 << 11) |
#define | BIOS_RLS (1 << 7) |
#define | SWSMI_TMR_EN (1 << 6) |
#define | APMC_EN (1 << 5) |
#define | SLP_SMI_EN (1 << 4) |
#define | LEGACY_USB_EN (1 << 3) |
#define | BIOS_EN (1 << 2) |
#define | EOS (1 << 1) |
#define | GBL_SMI_EN (1 << 0) |
#define | SMI_STS 0x34 |
#define | ALT_GP_SMI_EN 0x38 |
#define | ALT_GP_SMI_STS 0x3a |
#define | GPE_CNTL 0x42 |
#define | DEVACT_STS 0x44 |
#define | SS_CNT 0x50 |
#define | C3_RES 0x54 |
#define | TCO1_STS 0x64 |
#define | DMISCI_STS (1 << 9) |
#define | BOOT_STS (1 << 18) |
#define | TCO2_STS 0x66 |
#define | TCO1_CNT 0x68 |
#define | TCO_LOCK (1 << 12) |
#define | TCO2_CNT 0x6a |
Functions | |
u16 | get_pmbase (void) |
u16 | reset_pm1_status (void) |
read and clear PM1_STS More... | |
void | dump_pm1_status (u16 pm1_sts) |
void | dump_tco_status (u32 tco_sts) |
u32 | reset_tco_status (void) |
read and clear TCOx_STS More... | |
void | dump_gpe0_status (u64 gpe0_sts) |
u64 | reset_gpe0_status (void) |
read and clear GPE0_STS More... | |
void | dump_smi_status (u32 smi_sts) |
u32 | reset_smi_status (void) |
read and clear SMI_STS More... | |
void | gpe0_mask (u32 clr, u32 set) |
void | alt_gpi_mask (u16 clr, u16 set) |
void | smi_set_eos (void) |
Set the EOS bit. More... | |
void | dump_alt_gp_smi_status (u16 alt_gp_smi_sts) |
u16 | reset_alt_gp_smi_status (void) |
read and clear ALT_GP_SMI_STS More... | |
void | dump_all_status (void) |
void | southbridge_smm_xhci_sleep (u8 slp_type) |
void | gpi_route_interrupt (u8 gpi, u8 mode) |
void | southbridge_gate_memory_reset (void) |
void | southbridge_finalize_all (void) |
void | southbridge_smi_monitor (void) |
void | pch_log_state (void) |
Definition at line 11 of file pmutil.c.
References ALT_GP_SMI_EN, read_pmbase16(), and write_pmbase16().
Referenced by gpi_route_interrupt().
Definition at line 216 of file pmutil.c.
References dump_alt_gp_smi_status(), dump_gpe0_status(), dump_pm1_status(), dump_smi_status(), dump_tco_status(), reset_alt_gp_smi_status(), reset_gpe0_status(), reset_pm1_status(), reset_smi_status(), and reset_tco_status().
Referenced by global_smi_enable().
Definition at line 191 of file pmutil.c.
References BIOS_DEBUG, and printk.
Referenced by dump_all_status().
Definition at line 114 of file pmutil.c.
References BIOS_DEBUG, and printk.
Referenced by dump_all_status().
Definition at line 40 of file pmutil.c.
References BIOS_SPEW, PM1_EN, printk, and read_pmbase16().
Referenced by dump_all_status().
Definition at line 72 of file pmutil.c.
References BIOS_DEBUG, and printk.
Referenced by dump_all_status().
Definition at line 160 of file pmutil.c.
References BIOS_DEBUG, and printk.
Referenced by dump_all_status().
Definition at line 19 of file pmutil.c.
References GPE0_EN, read_pmbase32(), and write_pmbase32().
Referenced by gpi_route_interrupt().
Definition at line 25 of file smihandler.c.
References alt_gpi_mask(), D31F0_GPIO_ROUT, gpe0_mask(), GPI_IS_SCI, GPI_IS_SMI, PCI_DEV, pci_read_config32(), and pci_write_config32().
Referenced by mainboard_smi_apmc(), and mainboard_smi_sleep().
read and clear ALT_GP_SMI_STS
Definition at line 205 of file pmutil.c.
References ALT_GP_SMI_STS, read_pmbase16(), and write_pmbase16().
Referenced by dump_all_status(), and southbridge_smi_gpi().
read and clear GPE0_STS
Definition at line 101 of file pmutil.c.
References GPE0_STS, read_pmbase32(), and write_pmbase32().
Referenced by dump_all_status().
read and clear PM1_STS
Definition at line 31 of file pmutil.c.
References PM1_STS, read_pmbase16(), and write_pmbase16().
Referenced by clear_pm1_status(), and dump_all_status().
read and clear SMI_STS
Definition at line 61 of file pmutil.c.
References read_pmbase32(), SMI_STS, and write_pmbase32().
Referenced by clear_smi_status(), and dump_all_status().
read and clear TCOx_STS
Definition at line 144 of file pmutil.c.
References BOOT_STS, read_pmbase32(), TCO1_STS, and write_pmbase32().
Referenced by clear_tco_status(), and dump_all_status().
Set the EOS bit.
Definition at line 182 of file pmutil.c.
References EOS, read_pmbase8(), SMI_EN, and write_pmbase8().
Definition at line 215 of file smihandler.c.
References intel_ironlake_finalize_smm(), intel_me_finalize_smm(), intel_model_2065x_finalize_smm(), intel_model_206ax_finalize_smm(), intel_pch_finalize_smm(), and intel_sandybridge_finalize_smm().
Referenced by southbridge_smi_apmc().
Definition at line 69 of file smihandler.c.
References GP_IO_SEL, GP_IO_SEL2, GP_LVL, GP_LVL2, GPIO_USE_SEL, GPIO_USE_SEL2, GPIOBASE, PCH_LPC_DEV, PCI_DEV, pci_read_config16(), and southbridge_gate_memory_reset_real().
Referenced by southbridge_smi_sleep().
Definition at line 89 of file smihandler.c.
References BIOS_DEBUG, gnvs, io_trap_handler(), IOTRAP, mask, printk, RCBA32, and global_nvs::smif.
Definition at line 182 of file smihandler.c.
References ACPI_S3, ACPI_S4, ACPI_S5, FD, PCH_DISABLE_XHCI, PCH_LPC_DEV, pch_silicon_type(), PCH_TYPE_PPT, PCH_XHCI_DEV, pci_or_config16(), pci_read_config32(), RCBA, RCBA32, RCBA_ENABLE, xhci_a0_suspend_smm_workaround(), and XHCI_PWR_CNTL_STS.
Referenced by southbridge_smi_sleep().