coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
mainboard.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include "ec.h"
4 
5 #include <acpi/acpi.h>
6 #include <cpu/x86/smm.h>
7 #include <device/device.h>
9 
11 
12 static const u8 mainboard_picr_data[0x54] = {
13  0x1F, 0x1f, 0x1f, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
14  0x09, 0x1F, 0x1F, 0x0B, 0x1F, 0x0B, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
15  0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
16  0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
17  0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
18  0x1F, 0x1F, 0x1F, 0x1F
19 };
20 static const u8 mainboard_intr_data[0x54] = {
21  0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
22  0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
23  0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
24  0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
25  0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
26  0x10, 0x11, 0x12, 0x13
27 };
28 
29 static void pavilion_cold_boot_init(void)
30 {
31  /* Lid SMI is only used in non-ACPI mode; leave it off in S3 resume */
33  /* EC is not powered off during S3 sleep */
35 }
36 
37 /* PIRQ Setup */
38 static void pirq_setup(void)
39 {
42 }
43 
44 static void mainboard_enable(struct device *dev)
45 {
46  pirq_setup();
47 
50 
51  if (!acpi_is_wakeup_s3())
53 }
54 
57 };
struct chip_operations mainboard_ops
Definition: mainboard.c:19
static int acpi_is_wakeup_s3(void)
Definition: acpi.h:9
static const u8 mainboard_picr_data[0x54]
Definition: mainboard.c:12
static void pavilion_cold_boot_init(void)
Definition: mainboard.c:29
static const u8 mainboard_intr_data[0x54]
Definition: mainboard.c:20
static void mainboard_enable(struct device *dev)
Definition: mainboard.c:44
static void pirq_setup(void)
Definition: mainboard.c:38
#define EC_SMI_GEVENT
Definition: mainboard.h:13
#define EC_LID_GEVENT
Definition: mainboard.h:12
void global_smi_enable(void)
Set the EOS bit and enable SMI generation from southbridge.
Definition: smi_util.c:60
void pavilion_m6_1035dx_ec_init(void)
Definition: ec.c:20
const u8 * intr_data_ptr
Definition: amd_pci_util.c:13
const u8 * picr_data_ptr
Definition: amd_pci_util.c:14
@ SMI_MODE_SMI
Definition: smi.h:10
void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level)
Configure generation of interrupts for given GEVENT pin.
Definition: smi_util.c:43
@ SMI_LVL_LOW
Definition: smi.h:32
@ SMI_LVL_HIGH
Definition: smi.h:33
uint8_t u8
Definition: stdint.h:45
void(* enable_dev)(struct device *dev)
Definition: device.h:24
Definition: device.h:107