coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
usb.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <types.h>
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#ifndef _QCS405_USB_H_
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#define _QCS405_USB_H_
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/* QSCRATCH_GENERAL_CFG register bit offset */
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#define PIPE_UTMI_CLK_SEL BIT(0)
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#define PIPE3_PHYSTATUS_SW BIT(3)
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#define PIPE_UTMI_CLK_DIS BIT(8)
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/* Global USB3 Control Registers */
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#define DWC3_GUSB3PIPECTL_DELAYP1TRANS BIT(18)
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#define DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX BIT(27)
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#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
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#define DWC3_GCTL_PRTCAP_OTG 3
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#define DWC3_GCTL_PRTCAP_HOST 1
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/* Global USB2 PHY Configuration Register */
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#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10)
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#define DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
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#define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3)
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#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
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#define USBTRDTIM_UTMI_8_BIT 9
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#define UTMI_PHYIF_8_BIT 0
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#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
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#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
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#define DWC3_GCTL_DISSCRAMBLE (1 << 3)
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#define DWC3_GCTL_U2EXIT_LFPS (1 << 2)
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#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
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/* USB2 PHY register values */
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#define USB2PHY_TCSR_CTRL 0x01
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#define USB2PHY_REFCLK_CTRL 0x0d
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#define USB2PHY_UTMI_CTRL5 0x12
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#define USB2PHY_PARAMETER_OVERRIDE_X0 0x63
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#define USB2PHY_PARAMETER_OVERRIDE_X1 0x03
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#define USB2PHY_PARAMETER_OVERRIDE_X2 0x1d
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#define USB2PHY_PARAMETER_OVERRIDE_X3 0x03
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#define USB2PHY_HS_PHY_CTRL1 0x23
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#define QUSB2PHY_HS_PHY_CTRL_COMMON0 0x08
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#define QUSB2PHY_HS_PHY_CTRL_COMMON1 0xdc
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#define USB2PHY_HS_PHY_CTRL2 0xe0
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#define USB2PHY_UTMI_CTRL5_POR_CLEAR 0x10
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#define USB2PHY_HS_PHY_CTRL2_SUSPEND_N_SEL 0x60
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struct
usb_board_data
{
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/* Register values going to override from the boardfile */
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u8
parameter_override_x0
;
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u8
parameter_override_x1
;
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u8
parameter_override_x2
;
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u8
parameter_override_x3
;
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};
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enum
usb_port
{
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HSUSB_SS_PORT_0
,
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HSUSB_HS_PORT_1
,
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};
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void
setup_usb_host
(
enum
usb_port
port
,
struct
usb_board_data
*data);
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/* Call reset_ before setup_ */
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void
reset_usb
(
enum
usb_port
port
);
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#endif
/* _QCS405_USB_H_ */
port
port
Definition:
i915.h:29
setup_usb_host
void setup_usb_host(enum usb_port port, struct usb_board_data *data)
Definition:
usb.c:188
reset_usb
void reset_usb(enum usb_port port)
Definition:
usb.c:116
usb_port
usb_port
Definition:
usb.h:56
HSUSB_SS_PORT_0
@ HSUSB_SS_PORT_0
Definition:
usb.h:57
HSUSB_HS_PORT_1
@ HSUSB_HS_PORT_1
Definition:
usb.h:58
u8
uint8_t u8
Definition:
stdint.h:45
usb_board_data
Definition:
qusb_phy.h:42
usb_board_data::parameter_override_x2
u8 parameter_override_x2
Definition:
snps_usb_phy.h:10
usb_board_data::parameter_override_x0
u8 parameter_override_x0
Definition:
snps_usb_phy.h:8
usb_board_data::parameter_override_x3
u8 parameter_override_x3
Definition:
snps_usb_phy.h:11
usb_board_data::parameter_override_x1
u8 parameter_override_x1
Definition:
snps_usb_phy.h:9
src
soc
qualcomm
qcs405
include
soc
usb.h
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