coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.c
Go to the documentation of this file.
1
/* SPDX-License-Identifier: GPL-2.0-only */
2
3
#include <variant/gpio.h>
4
#include <baseboard/variants.h>
5
#include <
commonlib/helpers.h
>
6
7
/* Pad configuration in ramstage */
8
static
const
struct
pad_config
override_gpio_table
[] = {
9
/* A7 : I2S2_SCLK ==> I2S1_SPKR_SCLK */
10
PAD_CFG_NF
(
GPP_A7
,
NONE
, DEEP, NF1),
11
/* A8 : I2S2_SFRM ==> I2S1_SPKR_SFRM */
12
PAD_CFG_NF
(
GPP_A8
,
NONE
, DEEP, NF1),
13
/* A9 : I2S2_TXD ==> I2S1_PCH_TX_SPKR_RX */
14
PAD_CFG_NF
(
GPP_A9
,
NONE
, DEEP, NF1),
15
/* A10 : I2S2_RXD ==> I2S1_PCH_RX_SPKR */
16
PAD_CFG_NF
(
GPP_A10
,
NONE
, DEEP, NF1),
17
/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
18
PAD_CFG_GPO
(
GPP_A13
, 1, DEEP),
19
/* A16 : USB_OC3# ==> USB_C0_OC_ODL */
20
PAD_CFG_NF
(
GPP_A16
,
NONE
, DEEP, NF1),
21
/* A18 : DDSP_HPDB ==> HDMI_HPD */
22
PAD_CFG_NF
(
GPP_A18
,
NONE
, DEEP, NF1),
23
/* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */
24
PAD_CFG_NF
(
GPP_A19
,
NONE
, DEEP, NF1),
25
/* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */
26
PAD_CFG_NF
(
GPP_A20
,
NONE
, DEEP, NF1),
27
/* A21 : DDPC_CTRCLK ==> EN_FP_PWR */
28
PAD_CFG_GPO
(
GPP_A21
, 1, DEEP),
29
/* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */
30
PAD_CFG_GPO
(
GPP_A22
, 1, DEEP),
31
32
/* B2 : VRALERT# ==> NC */
33
PAD_NC
(
GPP_B2
,
NONE
),
34
/* B7 : ISH_12C1_SDA ==> ISH_I2C1_SENSOR_SDA */
35
PAD_CFG_NF
(
GPP_B7
,
NONE
, DEEP, NF1),
36
/* B8 : ISH_I2C1_SCL ==> ISH_I2C1_SENSOR_SCL */
37
PAD_CFG_NF
(
GPP_B8
,
NONE
, DEEP, NF1),
38
/* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */
39
PAD_CFG_NF
(
GPP_B9
,
NONE
, DEEP, NF1),
40
/* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */
41
PAD_CFG_NF
(
GPP_B10
,
NONE
, DEEP, NF1),
42
/* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
43
PAD_CFG_NF
(
GPP_B18
, DN_20K, DEEP, NF1),
44
/* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */
45
PAD_CFG_NF
(
GPP_B19
,
NONE
, DEEP, NF1),
46
/* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */
47
PAD_CFG_NF
(
GPP_B20
,
NONE
, DEEP, NF1),
48
/* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */
49
PAD_CFG_NF
(
GPP_B21
,
NONE
, DEEP, NF1),
50
/* B23 : SML1ALERT# ==> GPP_B23_STRAP # */
51
PAD_NC
(
GPP_B23
, DN_20K),
52
53
/* C0 : SMBCLK ==> EN_PP3300_WLAN */
54
PAD_CFG_GPO
(
GPP_C0
, 1, DEEP),
55
/* C2 : SMBALERT# ==> GPP_C2_STRAP */
56
PAD_NC
(
GPP_C2
, DN_20K),
57
/* C3 : SML0CLK ==> USB4_SMB_SCL */
58
PAD_CFG_NF
(
GPP_C3
,
NONE
, DEEP, NF1),
59
/* C4 : SML0DATA ==> USB4_SMB_SDA */
60
PAD_CFG_NF
(
GPP_C4
,
NONE
, DEEP, NF1),
61
/* C5 : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */
62
PAD_NC
(
GPP_C5
, DN_20K),
63
/* C7 : SML1DATA ==> EN_USI_CHARGE */
64
PAD_CFG_GPO
(
GPP_C7
, 1, DEEP),
65
/* C10 : UART0_RTS# ==> USI_RST_L */
66
PAD_CFG_GPO
(
GPP_C10
, 1, DEEP),
67
/* C13 : UART1_TXD ==> EN_PP5000_TRACKPAD */
68
PAD_CFG_GPO
(
GPP_C13
, 1, DEEP),
69
/* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */
70
PAD_CFG_NF
(
GPP_C16
,
NONE
, DEEP, NF1),
71
/* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */
72
PAD_CFG_NF
(
GPP_C17
,
NONE
, DEEP, NF1),
73
/* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */
74
PAD_CFG_NF
(
GPP_C18
,
NONE
, DEEP, NF1),
75
/* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */
76
PAD_CFG_NF
(
GPP_C19
,
NONE
, DEEP, NF1),
77
/* C20 : UART2_RXD ==> FPMCU_INT_L */
78
PAD_CFG_GPI_INT
(
GPP_C20
,
NONE
, PLTRST, LEVEL),
79
/* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
80
PAD_CFG_GPO
(
GPP_C22
, 0, DEEP),
81
/* C23 : UART2_CTS# ==> FPMCU_RST_ODL */
82
PAD_CFG_GPO
(
GPP_C23
, 1, DEEP),
83
84
/* D0 : ISH_GP0 ==> ISH_IMU_INT_L */
85
PAD_CFG_GPI
(
GPP_D0
,
NONE
, DEEP),
86
/* D1 : ISH_GP1 ==> ISH_ACCEL_INT_L */
87
PAD_CFG_GPI
(
GPP_D1
,
NONE
, DEEP),
88
/* D2 : ISH_GP2 ==> ISH_LID_OPEN */
89
PAD_CFG_GPI
(
GPP_D2
,
NONE
, DEEP),
90
/* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
91
PAD_CFG_NF
(
GPP_D8
,
NONE
, DEEP, NF1),
92
/* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */
93
PAD_CFG_NF
(
GPP_D10
, DN_20K, DEEP, NF7),
94
/* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */
95
PAD_CFG_NF
(
GPP_D12
, DN_20K, DEEP, NF7),
96
/* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */
97
PAD_CFG_NF
(
GPP_D13
,
NONE
, DEEP, NF1),
98
/* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */
99
PAD_CFG_NF
(
GPP_D14
,
NONE
, DEEP, NF1),
100
/* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
101
PAD_CFG_GPO
(
GPP_D16
, 1, DEEP),
102
103
/* E1 : SPI1_IO2 ==> PEN_DET_ODL */
104
PAD_CFG_GPI_SCI_LOW
(
GPP_E1
,
NONE
, DEEP, EDGE_SINGLE),
105
/* E3 : CPU_GP0 ==> USI_REPORT_EN */
106
PAD_CFG_GPO
(
GPP_E3
, 1, DEEP),
107
/* E7 : CPU_GP1 ==> USI_INT */
108
PAD_CFG_GPI_APIC
(
GPP_E7
,
NONE
, PLTRST, LEVEL,
NONE
),
109
/* E10 : SPI1_CS# ==> NC */
110
PAD_NC
(
GPP_E10
,
NONE
),
111
/* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */
112
PAD_CFG_GPI
(
GPP_E11
,
NONE
, DEEP),
113
/* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */
114
PAD_CFG_GPI
(
GPP_E12
,
NONE
, DEEP),
115
/* E13 : SPI1_MOSI_IO0 ==> NC */
116
PAD_NC
(
GPP_E13
,
NONE
),
117
/* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */
118
PAD_CFG_GPI_IRQ_WAKE(
GPP_E15
,
NONE
, DEEP, LEVEL, INVERT),
119
/* E16 : ISH_GP7 ==> USB_A0_RT_RST_ODL */
120
PAD_CFG_GPO
(
GPP_E16
, 1, DEEP),
121
/* E17 : THC0_SPI1_INT# ==> PEN_DET_ODL */
122
PAD_CFG_GPI_SCI_LOW
(
GPP_E1
,
NONE
, DEEP, EDGE_SINGLE),
123
/* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */
124
PAD_CFG_NF
(
GPP_E19
, DN_20K, DEEP, NF4),
125
126
/* F7 : GPPF7_STRAP */
127
PAD_NC
(
GPP_F7
, DN_20K),
128
/* F11 : THC1_SPI2_CLK ==> NC */
129
PAD_NC
(
GPP_F11
,
NONE
),
130
/* F12 : GSXDOUT ==> EN_PP3300_TRACKPAD */
131
PAD_CFG_GPO
(
GPP_F12
, 1, DEEP),
132
/* F13 : GSXDOUT ==> WiFi_DISABLE_L */
133
PAD_CFG_GPO
(
GPP_F13
, 1, DEEP),
134
/* F16 : GSXCLK ==> EN_PP3300_TOUCHSCREEN */
135
PAD_CFG_GPO
(
GPP_F16
, 1, DEEP),
136
/* F17 : WWAN_RF_DISABLE_ODL ==> EC_IN_RW_OD */
137
PAD_CFG_GPI
(
GPP_F17
,
NONE
, DEEP),
138
/* F18 : THC1_SPI2_INT# ==> EN_SPKR_PA */
139
PAD_CFG_GPO
(
GPP_F18
, 1, DEEP),
140
141
/* H0 : GPPH0_BOOT_STRAP1 */
142
PAD_NC
(
GPP_H0
, DN_20K),
143
/* H1 : GPPH1_BOOT_STRAP2 */
144
PAD_NC
(
GPP_H1
, DN_20K),
145
/* H2 : GPPH2_BOOT_STRAP3 */
146
PAD_NC
(
GPP_H2
, DN_20K),
147
/* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */
148
PAD_CFG_GPO
(
GPP_H3
, 1, DEEP),
149
/* H10 : SRCCLKREQ4# ==> USB_C_MIX_RT_FORCE_PWR */
150
PAD_CFG_GPO
(
GPP_H10
, 0, DEEP),
151
/* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */
152
PAD_CFG_GPI
(
GPP_H13
,
NONE
, DEEP),
153
/* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */
154
PAD_CFG_NF
(
GPP_H16
,
NONE
, DEEP, NF1),
155
/* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */
156
PAD_CFG_NF
(
GPP_H17
,
NONE
, DEEP, NF1),
157
/* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL_R */
158
PAD_CFG_GPI
(
GPP_H19
,
NONE
, DEEP),
159
160
/* R0 : HDA_BCLK ==> I2S0_HP_SCLK */
161
PAD_CFG_NF
(
GPP_R0
,
NONE
, DEEP, NF2),
162
/* R1 : HDA_SYNC ==> I2S0_HP_SFRM */
163
PAD_CFG_NF
(
GPP_R1
,
NONE
, DEEP, NF2),
164
/* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */
165
PAD_CFG_NF
(
GPP_R2
, DN_20K, DEEP, NF2),
166
/* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */
167
PAD_CFG_NF
(
GPP_R3
,
NONE
, DEEP, NF2),
168
/* R5 : HDA_SDI1 ==> HP_INT_L */
169
PAD_CFG_GPI_INT
(
GPP_R5
,
NONE
, PLTRST, EDGE_BOTH),
170
171
/* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */
172
PAD_CFG_NF
(
GPP_S0
,
NONE
, DEEP, NF1),
173
/* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */
174
PAD_CFG_NF
(
GPP_S1
,
NONE
, DEEP, NF1),
175
/* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */
176
PAD_CFG_NF
(
GPP_S2
,
NONE
, DEEP, NF1),
177
/* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */
178
PAD_CFG_NF
(
GPP_S3
,
NONE
, DEEP, NF1),
179
/* S6 : SNDW3_CLK ==> DMIC_CLK0 */
180
PAD_CFG_NF
(
GPP_S6
,
NONE
, DEEP, NF2),
181
/* S7 : SNDW3_DATA ==> DMIC_DATA0 */
182
PAD_CFG_NF
(
GPP_S7
,
NONE
, DEEP, NF2),
183
184
/* GPD6: SLP_A# ==> NC */
185
PAD_NC
(
GPD6
,
NONE
),
186
/* GPD9: SLP_WLAN# ==> SLP_WLAN_L */
187
PAD_CFG_NF
(
GPD9
,
NONE
, DEEP, NF1),
188
};
189
190
const
struct
pad_config
*
variant_override_gpio_table
(
size_t
*num)
191
{
192
*num =
ARRAY_SIZE
(
override_gpio_table
);
193
return
override_gpio_table
;
194
}
195
196
/* Early pad configuration in bootblock */
197
static
const
struct
pad_config
early_gpio_table
[] = {
198
/* C8 : UART0 RX */
199
PAD_CFG_NF
(
GPP_C8
,
NONE
, DEEP, NF1),
200
/* C9 : UART0 TX */
201
PAD_CFG_NF
(
GPP_C9
,
NONE
, DEEP, NF1),
202
203
/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
204
PAD_CFG_NF
(
GPP_A12
,
NONE
, DEEP, NF1),
205
/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
206
/* assert reset on reboot */
207
PAD_CFG_GPO
(
GPP_A13
, 0, DEEP),
208
/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
209
PAD_CFG_GPI
(
GPP_A17
,
NONE
, DEEP),
210
211
/* B11 : PMCALERT# ==> PCH_WP_OD */
212
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_B11
,
NONE
, DEEP),
213
/* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
214
PAD_CFG_NF
(
GPP_B15
,
NONE
, DEEP, NF1),
215
/* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */
216
PAD_CFG_NF
(
GPP_B16
,
NONE
, DEEP, NF1),
217
/* B17 : GSPI0_MISO ==> PCH_GSPI0_H1_TPM_MISO */
218
PAD_CFG_NF
(
GPP_B17
,
NONE
, DEEP, NF1),
219
/* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
220
PAD_CFG_NF
(
GPP_B18
, DN_20K, DEEP, NF1),
221
222
/* C0 : SMBCLK ==> EN_PP3300_WLAN */
223
PAD_CFG_GPO
(
GPP_C0
, 1, DEEP),
224
/* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
225
PAD_CFG_GPI_APIC
(
GPP_C21
,
NONE
, PLTRST, LEVEL, INVERT),
226
/* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
227
PAD_CFG_GPO
(
GPP_C22
, 0, DEEP),
228
229
/* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
230
PAD_CFG_GPO
(
GPP_D16
, 1, DEEP),
231
232
/* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */
233
PAD_CFG_GPI
(
GPP_E12
,
NONE
, DEEP),
234
235
/* F17 : WWAN_RF_DISABLE_ODL ==> EC_IN_RW_OD */
236
PAD_CFG_GPI
(
GPP_F17
,
NONE
, DEEP),
237
};
238
239
const
struct
pad_config
*
variant_early_gpio_table
(
size_t
*num)
240
{
241
*num =
ARRAY_SIZE
(
early_gpio_table
);
242
return
early_gpio_table
;
243
}
GPP_H19
#define GPP_H19
Definition:
gpio_soc_defs.h:235
GPP_D1
#define GPP_D1
Definition:
gpio_soc_defs.h:253
GPD9
#define GPD9
Definition:
gpio_soc_defs.h:390
GPP_C2
#define GPP_C2
Definition:
gpio_soc_defs.h:539
GPP_D10
#define GPP_D10
Definition:
gpio_soc_defs.h:262
GPP_D8
#define GPP_D8
Definition:
gpio_soc_defs.h:260
GPP_E3
#define GPP_E3
Definition:
gpio_soc_defs.h:631
GPP_A18
#define GPP_A18
Definition:
gpio_soc_defs.h:137
GPP_F12
#define GPP_F12
Definition:
gpio_soc_defs.h:585
GPP_F16
#define GPP_F16
Definition:
gpio_soc_defs.h:589
GPP_H16
#define GPP_H16
Definition:
gpio_soc_defs.h:232
GPP_D14
#define GPP_D14
Definition:
gpio_soc_defs.h:266
GPP_S0
#define GPP_S0
Definition:
gpio_soc_defs.h:160
GPP_C5
#define GPP_C5
Definition:
gpio_soc_defs.h:542
GPP_H17
#define GPP_H17
Definition:
gpio_soc_defs.h:233
GPP_D12
#define GPP_D12
Definition:
gpio_soc_defs.h:264
GPP_B16
#define GPP_B16
Definition:
gpio_soc_defs.h:69
GPP_B2
#define GPP_B2
Definition:
gpio_soc_defs.h:55
GPP_R3
#define GPP_R3
Definition:
gpio_soc_defs.h:672
GPP_A19
#define GPP_A19
Definition:
gpio_soc_defs.h:138
GPP_D2
#define GPP_D2
Definition:
gpio_soc_defs.h:254
GPP_C9
#define GPP_C9
Definition:
gpio_soc_defs.h:546
GPP_H2
#define GPP_H2
Definition:
gpio_soc_defs.h:218
GPP_C22
#define GPP_C22
Definition:
gpio_soc_defs.h:559
GPP_R0
#define GPP_R0
Definition:
gpio_soc_defs.h:669
GPP_B15
#define GPP_B15
Definition:
gpio_soc_defs.h:68
GPP_E13
#define GPP_E13
Definition:
gpio_soc_defs.h:641
GPP_C23
#define GPP_C23
Definition:
gpio_soc_defs.h:560
GPP_H13
#define GPP_H13
Definition:
gpio_soc_defs.h:229
GPP_C8
#define GPP_C8
Definition:
gpio_soc_defs.h:545
GPP_S7
#define GPP_S7
Definition:
gpio_soc_defs.h:167
GPP_H1
#define GPP_H1
Definition:
gpio_soc_defs.h:217
GPP_C18
#define GPP_C18
Definition:
gpio_soc_defs.h:555
GPP_S3
#define GPP_S3
Definition:
gpio_soc_defs.h:163
GPP_C13
#define GPP_C13
Definition:
gpio_soc_defs.h:550
GPP_C17
#define GPP_C17
Definition:
gpio_soc_defs.h:554
GPP_A7
#define GPP_A7
Definition:
gpio_soc_defs.h:126
GPP_B8
#define GPP_B8
Definition:
gpio_soc_defs.h:61
GPP_S1
#define GPP_S1
Definition:
gpio_soc_defs.h:161
GPP_C20
#define GPP_C20
Definition:
gpio_soc_defs.h:557
GPP_B20
#define GPP_B20
Definition:
gpio_soc_defs.h:73
GPP_A20
#define GPP_A20
Definition:
gpio_soc_defs.h:139
GPP_A16
#define GPP_A16
Definition:
gpio_soc_defs.h:135
GPP_F17
#define GPP_F17
Definition:
gpio_soc_defs.h:590
GPP_A12
#define GPP_A12
Definition:
gpio_soc_defs.h:131
GPP_C10
#define GPP_C10
Definition:
gpio_soc_defs.h:547
GPP_E7
#define GPP_E7
Definition:
gpio_soc_defs.h:635
GPP_C16
#define GPP_C16
Definition:
gpio_soc_defs.h:553
GPP_F7
#define GPP_F7
Definition:
gpio_soc_defs.h:580
GPP_F13
#define GPP_F13
Definition:
gpio_soc_defs.h:586
GPP_C4
#define GPP_C4
Definition:
gpio_soc_defs.h:541
GPP_S6
#define GPP_S6
Definition:
gpio_soc_defs.h:166
GPP_B19
#define GPP_B19
Definition:
gpio_soc_defs.h:72
GPP_E19
#define GPP_E19
Definition:
gpio_soc_defs.h:647
GPP_H0
#define GPP_H0
Definition:
gpio_soc_defs.h:215
GPP_C21
#define GPP_C21
Definition:
gpio_soc_defs.h:558
GPP_R2
#define GPP_R2
Definition:
gpio_soc_defs.h:671
GPP_B9
#define GPP_B9
Definition:
gpio_soc_defs.h:62
GPP_H3
#define GPP_H3
Definition:
gpio_soc_defs.h:219
GPP_A10
#define GPP_A10
Definition:
gpio_soc_defs.h:129
GPP_A8
#define GPP_A8
Definition:
gpio_soc_defs.h:127
GPP_D0
#define GPP_D0
Definition:
gpio_soc_defs.h:252
GPP_B11
#define GPP_B11
Definition:
gpio_soc_defs.h:64
GPP_D13
#define GPP_D13
Definition:
gpio_soc_defs.h:265
GPP_B18
#define GPP_B18
Definition:
gpio_soc_defs.h:71
GPP_R5
#define GPP_R5
Definition:
gpio_soc_defs.h:674
GPP_A9
#define GPP_A9
Definition:
gpio_soc_defs.h:128
GPP_E10
#define GPP_E10
Definition:
gpio_soc_defs.h:638
GPP_C19
#define GPP_C19
Definition:
gpio_soc_defs.h:556
GPP_A13
#define GPP_A13
Definition:
gpio_soc_defs.h:132
GPP_S2
#define GPP_S2
Definition:
gpio_soc_defs.h:162
GPP_A21
#define GPP_A21
Definition:
gpio_soc_defs.h:140
GPP_B23
#define GPP_B23
Definition:
gpio_soc_defs.h:76
GPP_E15
#define GPP_E15
Definition:
gpio_soc_defs.h:643
GPP_B10
#define GPP_B10
Definition:
gpio_soc_defs.h:63
GPP_E16
#define GPP_E16
Definition:
gpio_soc_defs.h:644
GPP_E11
#define GPP_E11
Definition:
gpio_soc_defs.h:639
GPD6
#define GPD6
Definition:
gpio_soc_defs.h:387
GPP_F18
#define GPP_F18
Definition:
gpio_soc_defs.h:591
GPP_A22
#define GPP_A22
Definition:
gpio_soc_defs.h:141
GPP_F11
#define GPP_F11
Definition:
gpio_soc_defs.h:584
GPP_B21
#define GPP_B21
Definition:
gpio_soc_defs.h:74
GPP_D16
#define GPP_D16
Definition:
gpio_soc_defs.h:268
GPP_H10
#define GPP_H10
Definition:
gpio_soc_defs.h:226
GPP_C3
#define GPP_C3
Definition:
gpio_soc_defs.h:540
GPP_E12
#define GPP_E12
Definition:
gpio_soc_defs.h:640
GPP_A17
#define GPP_A17
Definition:
gpio_soc_defs.h:136
GPP_B17
#define GPP_B17
Definition:
gpio_soc_defs.h:70
GPP_C0
#define GPP_C0
Definition:
gpio_soc_defs.h:537
GPP_E1
#define GPP_E1
Definition:
gpio_soc_defs.h:629
GPP_B7
#define GPP_B7
Definition:
gpio_soc_defs.h:60
GPP_C7
#define GPP_C7
Definition:
gpio_soc_defs.h:544
GPP_R1
#define GPP_R1
Definition:
gpio_soc_defs.h:670
ARRAY_SIZE
#define ARRAY_SIZE(a)
Definition:
helpers.h:12
helpers.h
variant_early_gpio_table
const struct pad_config * variant_early_gpio_table(size_t *num)
Definition:
gpio.c:204
variant_override_gpio_table
const struct pad_config *__weak variant_override_gpio_table(size_t *num)
Definition:
gpio.c:450
override_gpio_table
static const struct pad_config override_gpio_table[]
Definition:
gpio.c:8
early_gpio_table
static const struct pad_config early_gpio_table[]
Definition:
gpio.c:197
NONE
@ NONE
Definition:
qup_se_handlers_common.h:196
PAD_NC
#define PAD_NC(pin)
Definition:
gpio_defs.h:263
PAD_CFG_GPI
#define PAD_CFG_GPI(pad, pull, rst)
Definition:
gpio_defs.h:284
PAD_CFG_GPI_SCI_LOW
#define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig)
Definition:
gpio_defs.h:452
PAD_CFG_NF
#define PAD_CFG_NF(pad, pull, rst, func)
Definition:
gpio_defs.h:197
PAD_CFG_GPI_INT
#define PAD_CFG_GPI_INT(pad, pull, rst, trig)
Definition:
gpio_defs.h:348
PAD_CFG_GPI_APIC
#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv)
Definition:
gpio_defs.h:376
PAD_CFG_GPO
#define PAD_CFG_GPO(pad, val, rst)
Definition:
gpio_defs.h:247
PAD_CFG_GPI_GPIO_DRIVER
#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst)
Definition:
gpio_defs.h:323
pad_config
Definition:
gpio.h:75
src
mainboard
google
volteer
variants
todor
gpio.c
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