coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
heci.h
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef _SOC_APOLLOLAKE_HECI_H_
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#define _SOC_APOLLOLAKE_HECI_H_
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#include <
stdint.h
>
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enum
sec_status
{
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SEC_STATE_RESET
= 0,
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SEC_STATE_INIT
,
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SEC_STATE_RECOVERY
,
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SEC_STATE_UNKNOWN0
,
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SEC_STATE_UNKNOWN1
,
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SEC_STATE_NORMAL
,
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SEC_STATE_DISABLE_WAIT
,
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SEC_STATE_TRANSITION
,
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SEC_STATE_INVALID_CPU
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};
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#define REG_SEC_FW_STS0 0x40
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#define MASK_SEC_FIRMWARE_COMPLETE (1 << 9)
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#define MASK_SEC_STATUS 0xf
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/* Read Firmware Status register */
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uint32_t
heci_fw_sts
(
void
);
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/* Returns true if CSE is in normal status */
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bool
heci_cse_normal
(
void
);
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/* Returns true if CSE is done with whatever it was doing */
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bool
heci_cse_done
(
void
);
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/* Dump CSE state and lockdown HECI1 interface using P2SB message. */
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void
heci_cse_lockdown
(
void
);
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#endif
heci_cse_lockdown
void heci_cse_lockdown(void)
Definition:
cse.c:201
heci_cse_normal
bool heci_cse_normal(void)
Definition:
heci.c:14
heci_fw_sts
uint32_t heci_fw_sts(void)
Definition:
heci.c:9
heci_cse_done
bool heci_cse_done(void)
Definition:
heci.c:19
sec_status
sec_status
Definition:
heci.h:8
SEC_STATE_UNKNOWN1
@ SEC_STATE_UNKNOWN1
Definition:
heci.h:13
SEC_STATE_DISABLE_WAIT
@ SEC_STATE_DISABLE_WAIT
Definition:
heci.h:15
SEC_STATE_NORMAL
@ SEC_STATE_NORMAL
Definition:
heci.h:14
SEC_STATE_TRANSITION
@ SEC_STATE_TRANSITION
Definition:
heci.h:16
SEC_STATE_INIT
@ SEC_STATE_INIT
Definition:
heci.h:10
SEC_STATE_RECOVERY
@ SEC_STATE_RECOVERY
Definition:
heci.h:11
SEC_STATE_INVALID_CPU
@ SEC_STATE_INVALID_CPU
Definition:
heci.h:17
SEC_STATE_UNKNOWN0
@ SEC_STATE_UNKNOWN0
Definition:
heci.h:12
SEC_STATE_RESET
@ SEC_STATE_RESET
Definition:
heci.h:9
stdint.h
uint32_t
unsigned int uint32_t
Definition:
stdint.h:14
src
soc
intel
apollolake
include
soc
heci.h
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