![]() |
coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
|
Go to the source code of this file.
Macros | |
#define | SWINF_FSM_IDLE 0x00 |
#define | SWINF_FSM_REQ 0x02 |
#define | SWINF_FSM_WFDLE 0x04 |
#define | SWINF_FSM_WFVLDCLR 0x06 |
#define | SWINF_INIT_DONE 0x01 |
#define | GET_SWINF_0_FSM(x) (((x) >> 1) & 0x7) |
Enumerations | |
enum | { PMIF_READ_US = 1000 , PMIF_WAIT_IDLE_US = 1000 } |
enum | { CAL_TOL_RATE = 40 , CAL_MAX_VAL = 0x7F } |
Functions | |
u32 | pmif_get_ulposc_freq_mhz (u32 cali_val) |
int | pmif_clk_init (void) |
int pmif_clk_init | ( | void | ) |
Definition at line 105 of file pmif_clk.c.
References E_NODEV, mt8192_infracfg_regs::infra_globalcon_rst2_clr, mt8195_infracfg_ao_regs::infra_globalcon_rst2_clr, mt8192_infracfg_regs::infra_globalcon_rst2_set, mt8195_infracfg_ao_regs::infra_globalcon_rst2_set, mt8192_infracfg_regs::module_sw_cg_0_clr, mt8195_infracfg_ao_regs::module_sw_cg_0_clr, mt8192_infracfg_regs::module_sw_cg_0_set, mt8195_infracfg_ao_regs::module_sw_cg_0_set, mt8192_infracfg, mt8195_infracfg_ao, mtk_topckgen, mt8192_infracfg_regs::pmicw_clock_ctrl_clr, mt8195_infracfg_ao_regs::pmicw_clock_ctrl_clr, pmif_init_ulposc(), and SET32_BITFIELDS.
Referenced by mtk_pmif_init().
Definition at line 75 of file pmif_clk.c.
References FMETER_ABIST, FREQ_METER_ABIST_AD_OSC_CK, mt_fmeter_get_freq_khz(), mtk_apmixed, SET32_BITFIELDS, and udelay().
Referenced by pmif_ulposc_cali().