14 #include <soc/addressmap.h>
15 #include <soc/infracfg.h>
16 #include <soc/mcucfg.h>
87 #define MUX(_id, _reg, _mux_shift, _mux_width) \
89 .reg = &mtk_topckgen->_reg, \
90 .mux_shift = _mux_shift, \
91 .mux_width = _mux_width, \
94 #define MUX_UPD(_id, _reg, _mux_shift, _mux_width, _upd_reg, _upd_shift)\
96 .reg = &mtk_topckgen->_reg, \
97 .set_reg = &mtk_topckgen->_reg##_set, \
98 .clr_reg = &mtk_topckgen->_reg##_clr, \
99 .mux_shift = _mux_shift, \
100 .mux_width = _mux_width, \
101 .upd_reg = &mtk_topckgen->_upd_reg, \
102 .upd_shift = _upd_shift, \
299 static const struct pll plls[] = {
310 23, 22, mainpll_con1, 24, mainpll_con1, 0,
313 23, 22, univpll_con1, 24, univpll_con1, 0,
441 INFRACFG_AO_AUDIO_BUS_REG0, 0,
442 INFRACFG_AO_ICUSB_BUS_REG0, 0,
443 INFRACFG_AO_AUDIO_BUS_REG0, 1,
444 INFRACFG_AO_ICUSB_BUS_REG0, 1);
448 INFRACFG_AO_INFRA_BUS_REG0_0, 0,
449 INFRACFG_AO_INFRA_BUS_REG0_1, 0,
450 INFRACFG_AO_INFRA_BUS_REG0_2, 0,
451 INFRACFG_AO_INFRA_BUS_REG0_0, 0x603,
452 INFRACFG_AO_INFRA_BUS_REG0_1, 0xF,
453 INFRACFG_AO_INFRA_BUS_REG0_2, 1);
457 INFRACFG_AO_P2P_RX_CLK_REG0_MASK_0, 0,
458 INFRACFG_AO_P2P_RX_CLK_REG0_MASK_1, 0,
459 INFRACFG_AO_P2P_RX_CLK_REG0_MASK_1, 1);
463 INFRACFG_AO_PERI_BUS_REG0_0, 0,
464 INFRACFG_AO_PERI_BUS_REG0_1, 0,
465 INFRACFG_AO_PERI_BUS_REG0_2, 0,
466 INFRACFG_AO_PERI_BUS_REG0_0, 3,
467 INFRACFG_AO_PERI_BUS_REG0_1, 0xFF07C,
468 INFRACFG_AO_PERI_BUS_REG0_2, 1);
521 u32 output,
count, clk_dbg_cfg, clk_misc_cfg_0, clk26cali_0, clk26cali_1;
532 CLK_DBG_CFG_ABIST_CK_SEL,
id,
533 CLK_DBG_CFG_CKGEN_CK_SEL, 0,
534 CLK_DBG_CFG_METER_CK_SEL, 0);
536 CLK_MISC_CFG_0_METER_DIV, 1);
539 CLK_DBG_CFG_ABIST_CK_SEL, 0,
540 CLK_DBG_CFG_CKGEN_CK_SEL,
id,
541 CLK_DBG_CFG_METER_CK_SEL, 1);
543 CLK_MISC_CFG_0_METER_DIV, 0);
545 die(
"unsupport fmeter type\n");
557 output = (
count * 26000) / 1024;
static void write32(void *addr, uint32_t val)
static uint32_t read32(const void *addr)
void mux_set_sel(const struct mux *mux, u32 sel)
int pll_set_rate(const struct pll *pll, u32 rate)
void __noreturn die(const char *fmt,...)
#define setbits32(addr, set)
#define SET32_BITFIELDS(addr,...)
#define READ32_BITFIELD(addr, name)
#define clrsetbits32(addr, clear, set)
#define clrbits32(addr, clear)
#define wait_us(timeout_us, condition)
void mt_pll_raise_little_cpu_freq(u32 freq)
void pll_set_pcw_change(const struct pll *pll)
static struct mt8186_infracfg_ao_regs *const mt8186_infracfg_ao
static struct mt8186_mcucfg_regs *const mtk_mcucfg
static const struct mux muxes[]
static const struct rate rates[]
#define MUX_UPD(_id, _reg, _mux_shift, _mux_width, _upd_reg, _upd_shift)
static const struct mux_sel mux_sels[]
u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id)
void mt_pll_raise_cci_freq(u32 freq)
static const struct pll plls[]
#define PLL(_id, _reg, _pwr_reg, _rstb, _pcwbits, _div_reg, _div_shift, _pcw_reg, _pcw_shift, _div_rate)