gpio.c

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/* SPDX-License-Identifier: GPL-2.0-only */
 
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <commonlib/helpers.h>
 
static const struct pad_config gpio_table[] = {
        /* A0  : SAR0_INT_ODL */
        PAD_CFG_GPI_INT(GPP_A0, NONE, PLTRST, LEVEL),
        /* A6  : SAR1_INT_ODL */
        PAD_CFG_GPI_INT(GPP_A6, NONE, PLTRST, LEVEL),
        /* A8  : PEN_GARAGE_DET_L (wake) */
        PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE),
        /* A10 : FPMCU_PCH_BOOT1 */
        PAD_CFG_GPO(GPP_A10, 0, DEEP),
        /* A11 : PCH_SPI_FPMCU_CS_L */
        PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2),
        /* A12 : FPMCU_RST_ODL */
        PAD_CFG_GPO(GPP_A12, 0, DEEP),
        /* C13 : EC_PCH_INT_L */
        PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT),
        /* C15 : WWAN_DPR_SAR_ODL
         *
         * TODO: Driver doesn't use this pin as of now. In case driver starts
         * using this pin, expose this pin to driver.
         */
        PAD_CFG_GPO(GPP_C15, 1, DEEP),
};
 
const struct pad_config *override_gpio_table(size_t *num)
{
        *num = ARRAY_SIZE(gpio_table);
        return gpio_table;
}
 
/*
 * GPIOs configured before ramstage
 * Note: the Hatch platform's romstage will configure
 * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins
 * as inputs before it reads them, so they are not
 * needed in this table.
 */
static const struct pad_config early_gpio_table[] = {
        /* B15 : H1_SLAVE_SPI_CS_L */
        PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
        /* B16 : H1_SLAVE_SPI_CLK */
        PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
        /* B17 : H1_SLAVE_SPI_MISO_R */
        PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
        /* B18 : H1_SLAVE_SPI_MOSI_R */
        PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
        /* C8  : UART_PCH_RX_DEBUG_TX */
        PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
        /* C9  : UART_PCH_TX_DEBUG_RX */
        PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
        /* C14 : BT_DISABLE_L */
        PAD_CFG_GPO(GPP_C14, 0, DEEP),
        /* PCH_WP_OD */
        PAD_CFG_GPI(GPP_C20, NONE, DEEP),
        /* C21 : H1_PCH_INT_ODL */
        PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
        /* C22 : EC_IN_RW_OD */
        PAD_CFG_GPI(GPP_C22, NONE, DEEP),
        /* C23 : WLAN_PE_RST# */
        PAD_CFG_GPO(GPP_C23, 1, DEEP),
        /* E1  : M2_SSD_PEDET */
        PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
        /* E5  : SATA_DEVSLP1 */
        PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
        /* F2  : MEM_CH_SEL */
        PAD_CFG_GPI(GPP_F2, NONE, PLTRST),
};
 
const struct pad_config *variant_early_gpio_table(size_t *num)
{
        *num = ARRAY_SIZE(early_gpio_table);
        return early_gpio_table;
}