dmc_init_ddr3.c File Reference

#include <device/mmio.h>
#include <console/console.h>
#include <delay.h>
#include <soc/clk.h>
#include <soc/cpu.h>
#include <soc/dmc.h>
#include <soc/setup.h>

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Macros
#define	RDLVL_COMPLETE_TIMEOUT   10000

Functions
static void	reset_phy_ctrl (void)
int	ddr3_mem_ctrl_init (struct mem_timings *mem, unsigned long mem_iv_size, int mem_reset)

Macro Definition Documentation

RDLVL_COMPLETE_TIMEOUT

#define RDLVL_COMPLETE_TIMEOUT   10000

Definition at line 13 of file dmc_init_ddr3.c.

Function Documentation

ddr3_mem_ctrl_init()

int ddr3_mem_ctrl_init	(	struct mem_timings *	mem,
		unsigned long	mem_iv_size,
		int	mem_reset
	)

Definition at line 25 of file dmc_init_ddr3.c.

References mem_timings::aref_en, BIOS_EMERG, BYTE_RDLVL_EN, CA_ADR_DRVR_DS_OFFSET, CA_CK_DRVR_DS_OFFSET, CA_CKE_DRVR_DS_OFFSET, CA_CS_DRVR_DS_OFFSET, exynos5_dmc::concontrol, mem_timings::concontrol, CONCONTROL_AREF_EN_SHIFT, CONCONTROL_DFI_INIT_START_SHIFT, CONCONTROL_RD_FETCH_SHIFT, mem_timings::ctrl_bstlen, mem_timings::ctrl_dll_on, mem_timings::ctrl_force, CTRL_GATEDURADJ_MASK, mem_timings::ctrl_inc, mem_timings::ctrl_rdlat, CTRL_RDLVL_GATE_DISABLE, CTRL_RDLVL_GATE_ENABLE, mem_timings::ctrl_ref, CTRL_SHGATE, mem_timings::ctrl_start, mem_timings::ctrl_start_point, DDR_MODE_DDR3, mem_timings::dfi_init_start, dmc_config_mrs(), dmc_config_prech(), dmc_config_zq(), DMC_MEMCONTROL_DSREF_ENABLE, mem_timings::dpwrdn_cyc, mem_timings::dsref_cyc, exynos_dmc, exynos_phy0_control, exynos_phy1_control, mem_timings::gate_leveling_enable, mem_timings::impedance, INIT_DESKEW_EN, mem_timings::iv_size, exynos5_dmc::ivcontrol, exynos5_dmc::membaseconfig0, mem_timings::membaseconfig0, exynos5_dmc::membaseconfig1, mem_timings::membaseconfig1, mem_timings::memconfig, exynos5_dmc::memconfig0, exynos5_dmc::memconfig1, exynos5_dmc::memcontrol, mem_timings::memcontrol, P0_CMD_EN, mem_timings::phy0_dq, mem_timings::phy0_dqs, mem_timings::phy0_pulld_dqs, mem_timings::phy0_tFS, mem_timings::phy1_dq, mem_timings::phy1_dqs, mem_timings::phy1_pulld_dqs, mem_timings::phy1_tFS, exynos5_phy_control::phy_con0, PHY_CON0_RESET_VAL, exynos5_phy_control::phy_con1, exynos5_phy_control::phy_con10, exynos5_phy_control::phy_con12, PHY_CON12_CTRL_DLL_ON_SHIFT, PHY_CON12_CTRL_FORCE_SHIFT, PHY_CON12_CTRL_INC_SHIFT, PHY_CON12_CTRL_REF_SHIFT, PHY_CON12_CTRL_START_POINT_SHIFT, PHY_CON12_CTRL_START_SHIFT, exynos5_phy_control::phy_con14, PHY_CON1_RESET_VAL, exynos5_phy_control::phy_con2, PHY_CON2_RESET_VAL, exynos5_phy_control::phy_con39, exynos5_phy_control::phy_con4, exynos5_phy_control::phy_con42, PHY_CON42_CTRL_BSTLEN_SHIFT, PHY_CON42_CTRL_RDLAT_SHIFT, exynos5_phy_control::phy_con6, exynos5_dmc::phystatus, exynos5_dmc::prechconfig, mem_timings::prechconfig_tp_cnt, PRECHCONFIG_TP_CNT_SHIFT, printk, exynos5_dmc::pwrdnconfig, PWRDNCONFIG_DPWRDN_CYC_SHIFT, PWRDNCONFIG_DSREF_CYC_SHIFT, mem_timings::rd_fetch, RDLVL_COMPLETE_CH1, RDLVL_COMPLETE_CHO, RDLVL_COMPLETE_TIMEOUT, exynos5_dmc::rdlvl_config, RDLVL_GATE_EN, read32(), reset_phy_ctrl(), SETUP_ERR_RDLV_COMPLETE_TIMEOUT, SETUP_ERR_ZQ_CALIBRATION_FAILURE, mem_timings::timing_data, mem_timings::timing_power, mem_timings::timing_ref, mem_timings::timing_row, exynos5_dmc::timingdata, exynos5_dmc::timingpower, exynos5_dmc::timingref, exynos5_dmc::timingrow, udelay(), update_reset_dll(), val, and write32().

Referenced by setup_memory().

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reset_phy_ctrl()

static void reset_phy_ctrl ( void  )

static

Definition at line 15 of file dmc_init_ddr3.c.

References exynos_clock, exynos5_clock::lpddr3phy_ctrl, LPDDR3PHY_CTRL_PHY_RESET_DISABLE, LPDDR3PHY_CTRL_PHY_RESET_ENABLE, udelay(), and write32().

Referenced by ddr3_mem_ctrl_init().

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