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clk.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef CPU_SAMSUNG_EXYNOS5250_CLK_H
4 #define CPU_SAMSUNG_EXYNOS5250_CLK_H
5 
6 #include <soc/cpu.h>
7 #include <soc/dmc.h>
8 #include <soc/pinmux.h>
9 #include <stdint.h>
10 
11 enum periph_id;
12 
13 #define APLL 0
14 #define MPLL 1
15 #define EPLL 2
16 #define HPLL 3
17 #define VPLL 4
18 #define BPLL 5
19 
20 enum pll_src_bit {
21  SRC_MPLL = 6,
22  SRC_EPLL,
23  SRC_VPLL,
24 };
25 
26 /* *
27  * This structure is to store the src bit, div bit and prediv bit
28  * positions of the peripheral clocks of the src and div registers
29  */
30 struct clk_bit_info {
31  s8 src_bit; /* offset in register to clock source field */
32  s8 n_src_bits; /* number of bits in 'src_bit' field */
33  s8 div_bit;
34  s8 prediv_bit;
35 };
36 
37 unsigned long get_pll_clk(int pllreg);
38 unsigned long get_arm_clk(void);
39 unsigned long get_pwm_clk(void);
40 unsigned long get_uart_clk(int dev_index);
41 void set_mmc_clk(int dev_index, unsigned int div);
42 
43 /**
44  * get the clk frequency of the required peripheral
45  *
46  * @param peripheral Peripheral id
47  *
48  * @return frequency of the peripheral clk
49  */
50 unsigned long clock_get_periph_rate(enum periph_id peripheral);
51 
52 #define MCT_HZ 24000000
53 
54 /*
55  * Set mshci controller instances clock divider
56  *
57  * @param enum periph_id instance of the mshci controller
58  *
59  * Return 0 if ok else -1
60  */
61 int clock_set_mshci(enum periph_id peripheral);
62 
63 /*
64  * Sets the epll clockrate
65  *
66  * @param rate Required clock rate to the prescaler in Hz
67  *
68  * Return 0 if ok else -1
69  */
70 int clock_epll_set_rate(unsigned long rate);
71 
72 /*
73  * selects the clk source for I2S MCLK
74  */
75 void clock_select_i2s_clk_source(void);
76 
77 /*
78  * Set prescaler division based on input and output frequency
79  * for i2s audio clock
80  *
81  * @param src_frq Source frequency in Hz
82  * @param dst_frq Required MCLK frequency in Hz
83  *
84  * Return 0 if ok else -1
85  */
86 int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq);
87 
88 struct exynos5_clock {
89  unsigned int apll_lock; /* base + 0 */
90  unsigned char res1[0xfc];
91  unsigned int apll_con0;
92  unsigned int apll_con1;
93  unsigned char res2[0xf8];
94  unsigned int src_cpu;
95  unsigned char res3[0x1fc];
96  unsigned int mux_stat_cpu;
97  unsigned char res4[0xfc];
98  unsigned int div_cpu0;
99  unsigned int div_cpu1;
100  unsigned char res5[0xf8];
101  unsigned int div_stat_cpu0;
102  unsigned int div_stat_cpu1;
103  unsigned char res6[0x1f8];
104  unsigned int gate_sclk_cpu;
105  unsigned char res7[0x1fc];
106  unsigned int clkout_cmu_cpu;
107  unsigned int clkout_cmu_cpu_div_stat;
108  unsigned char res8[0x5f8];
109 
110  unsigned int armclk_stopctrl; /* base + 0x1000 */
111  unsigned int atclk_stopctrl;
112  unsigned char res9[0x8];
113  unsigned int parityfail_status;
114  unsigned int parityfail_clear;
115  unsigned char res10[0x8];
116  unsigned int pwr_ctrl;
117  unsigned int pwr_ctr2;
118  unsigned char res11[0xd8];
119  unsigned int apll_con0_l8;
120  unsigned int apll_con0_l7;
121  unsigned int apll_con0_l6;
122  unsigned int apll_con0_l5;
123  unsigned int apll_con0_l4;
124  unsigned int apll_con0_l3;
125  unsigned int apll_con0_l2;
126  unsigned int apll_con0_l1;
127  unsigned int iem_control;
128  unsigned char res12[0xdc];
129  unsigned int apll_con1_l8;
130  unsigned int apll_con1_l7;
131  unsigned int apll_con1_l6;
132  unsigned int apll_con1_l5;
133  unsigned int apll_con1_l4;
134  unsigned int apll_con1_l3;
135  unsigned int apll_con1_l2;
136  unsigned int apll_con1_l1;
137  unsigned char res13[0xe0];
138  unsigned int div_iem_l8;
139  unsigned int div_iem_l7;
140  unsigned int div_iem_l6;
141  unsigned int div_iem_l5;
142  unsigned int div_iem_l4;
143  unsigned int div_iem_l3;
144  unsigned int div_iem_l2;
145  unsigned int div_iem_l1;
146  unsigned char res14[0x2ce0];
147 
148  unsigned int mpll_lock; /* base + 0x4000 */
149  unsigned char res15[0xfc];
150  unsigned int mpll_con0;
151  unsigned int mpll_con1;
152  unsigned char res16[0xf8];
153  unsigned int src_core0;
154  unsigned int src_core1;
155  unsigned char res17[0xf8];
156  unsigned int src_mask_core;
157  unsigned char res18[0x100];
158  unsigned int mux_stat_core1;
159  unsigned char res19[0xf8];
160  unsigned int div_core0;
161  unsigned int div_core1;
162  unsigned int div_sysrgt;
163  unsigned char res20[0xf4];
164  unsigned int div_stat_core0;
165  unsigned int div_stat_core1;
166  unsigned int div_stat_sysrgt;
167  unsigned char res21[0x2f4];
168  unsigned int gate_ip_core;
169  unsigned int gate_ip_sysrgt;
170  unsigned char res22[0xf8];
171  unsigned int clkout_cmu_core;
172  unsigned int clkout_cmu_core_div_stat;
173  unsigned char res23[0x5f8];
174 
175  unsigned int dcgidx_map0; /* base + 0x5000 */
176  unsigned int dcgidx_map1;
177  unsigned int dcgidx_map2;
178  unsigned char res24[0x14];
179  unsigned int dcgperf_map0;
180  unsigned int dcgperf_map1;
181  unsigned char res25[0x18];
182  unsigned int dvcidx_map;
183  unsigned char res26[0x1c];
184  unsigned int freq_cpu;
185  unsigned int freq_dpm;
186  unsigned char res27[0x18];
187  unsigned int dvsemclk_en;
188  unsigned int maxperf;
189  unsigned char res28[0x3478];
190 
191  unsigned int div_acp; /* base + 0x8500 */
192  unsigned char res29[0xfc];
193  unsigned int div_stat_acp;
194  unsigned char res30[0x1fc];
195  unsigned int gate_ip_acp;
196  unsigned char res31a[0xfc];
197  unsigned int div_syslft;
198  unsigned char res31b[0xc];
199  unsigned int div_stat_syslft;
200  unsigned char res31c[0xc];
201  unsigned int gate_bus_syslft;
202  unsigned char res31d[0xdc];
203  unsigned int clkout_cmu_acp;
204  unsigned int clkout_cmu_acp_div_stat;
205  unsigned char res32[0x38f8];
206 
207  unsigned int div_isp0; /* base + 0xc300 */
208  unsigned int div_isp1;
209  unsigned int div_isp2;
210  unsigned char res33[0xf4];
211 
212  unsigned int div_stat_isp0; /* base + 0xc400 */
213  unsigned int div_stat_isp1;
214  unsigned int div_stat_isp2;
215  unsigned char res34[0x3f4];
216 
217  unsigned int gate_ip_isp0; /* base + 0xc800 */
218  unsigned int gate_ip_isp1;
219  unsigned char res35[0xf8];
220  unsigned int gate_sclk_isp;
221  unsigned char res36[0xc];
222  unsigned int mcuisp_pwr_ctrl;
223  unsigned char res37[0xec];
224  unsigned int clkout_cmu_isp;
225  unsigned int clkout_cmu_isp_div_stat;
226  unsigned char res38[0x3618];
227 
228  unsigned int cpll_lock; /* base + 0x10020 */
229  unsigned char res39[0xc];
230  unsigned int epll_lock;
231  unsigned char res40[0xc];
232  unsigned int vpll_lock;
233  unsigned char res41a[0xc];
234  unsigned int gpll_lock;
235  unsigned char res41b[0xcc];
236  unsigned int cpll_con0;
237  unsigned int cpll_con1;
238  unsigned char res42[0x8];
239  unsigned int epll_con0;
240  unsigned int epll_con1;
241  unsigned int epll_con2;
242  unsigned char res43[0x4];
243  unsigned int vpll_con0;
244  unsigned int vpll_con1;
245  unsigned int vpll_con2;
246  unsigned char res44a[0x4];
247  unsigned int gpll_con0;
248  unsigned int gpll_con1;
249  unsigned char res44b[0xb8];
250  unsigned int src_top0;
251  unsigned int src_top1;
252  unsigned int src_top2;
253  unsigned int src_top3;
254  unsigned int src_gscl;
255  unsigned int src_disp0_0;
256  unsigned int src_disp0_1;
257  unsigned int src_disp1_0;
258  unsigned int src_disp1_1;
259  unsigned char res46[0xc];
260  unsigned int src_mau;
261  unsigned int src_fsys;
262  unsigned char res47[0x8];
263  unsigned int src_peric0;
264  unsigned int src_peric1;
265  unsigned char res48[0x18];
266  unsigned int sclk_src_isp;
267  unsigned char res49[0x9c];
268  unsigned int src_mask_top;
269  unsigned char res50[0xc];
270  unsigned int src_mask_gscl;
271  unsigned int src_mask_disp0_0;
272  unsigned int src_mask_disp0_1;
273  unsigned int src_mask_disp1_0;
274  unsigned int src_mask_disp1_1;
275  unsigned int src_mask_maudio;
276  unsigned char res52[0x8];
277  unsigned int src_mask_fsys;
278  unsigned char res53[0xc];
279  unsigned int src_mask_peric0;
280  unsigned int src_mask_peric1;
281  unsigned char res54[0x18];
282  unsigned int src_mask_isp;
283  unsigned char res55[0x9c];
284  unsigned int mux_stat_top0;
285  unsigned int mux_stat_top1;
286  unsigned int mux_stat_top2;
287  unsigned int mux_stat_top3;
288  unsigned char res56[0xf0];
289  unsigned int div_top0;
290  unsigned int div_top1;
291  unsigned char res57[0x8];
292  unsigned int div_gscl;
293  unsigned int div_disp0_0;
294  unsigned int div_disp0_1;
295  unsigned int div_disp1_0;
296  unsigned int div_disp1_1;
297  unsigned char res59[0x8];
298  unsigned int div_gen;
299  unsigned char res60[0x4];
300  unsigned int div_mau;
301  unsigned int div_fsys0;
302  unsigned int div_fsys1;
303  unsigned int div_fsys2;
304  unsigned int div_fsys3;
305  unsigned int div_peric0;
306  unsigned int div_peric1;
307  unsigned int div_peric2;
308  unsigned int div_peric3;
309  unsigned int div_peric4;
310  unsigned int div_peric5;
311  unsigned char res61[0x10];
312  unsigned int sclk_div_isp;
313  unsigned char res62[0xc];
314  unsigned int div2_ratio0;
315  unsigned int div2_ratio1;
316  unsigned char res63[0x8];
317  unsigned int div4_ratio;
318  unsigned char res64[0x6c];
319  unsigned int div_stat_top0;
320  unsigned int div_stat_top1;
321  unsigned char res65[0x8];
322  unsigned int div_stat_gscl;
323  unsigned int div_stat_disp0_0;
324  unsigned int div_stat_disp0_1;
325  unsigned int div_stat_disp1_0;
326  unsigned int div_stat_disp1_1;
327  unsigned char res67[0x8];
328  unsigned int div_stat_gen;
329  unsigned char res68[0x4];
330  unsigned int div_stat_maudio;
331  unsigned int div_stat_fsys0;
332  unsigned int div_stat_fsys1;
333  unsigned int div_stat_fsys2;
334  unsigned int div_stat_fsys3;
335  unsigned int div_stat_peric0;
336  unsigned int div_stat_peric1;
337  unsigned int div_stat_peric2;
338  unsigned int div_stat_peric3;
339  unsigned int div_stat_peric4;
340  unsigned int div_stat_peric5;
341  unsigned char res69[0x10];
342  unsigned int sclk_div_stat_isp;
343  unsigned char res70[0xc];
344  unsigned int div2_stat0;
345  unsigned int div2_stat1;
346  unsigned char res71[0x8];
347  unsigned int div4_stat;
348  unsigned char res72[0x180];
349  unsigned int gate_top_sclk_disp0;
350  unsigned int gate_top_sclk_disp1;
351  unsigned int gate_top_sclk_gen;
352  unsigned char res74[0xc];
353  unsigned int gate_top_sclk_mau;
354  unsigned int gate_top_sclk_fsys;
355  unsigned char res75[0xc];
356  unsigned int gate_top_sclk_peric;
357  unsigned char res76[0x1c];
358  unsigned int gate_top_sclk_isp;
359  unsigned char res77[0xac];
360  unsigned int gate_ip_gscl;
361  unsigned int gate_ip_disp0;
362  unsigned int gate_ip_disp1;
363  unsigned int gate_ip_mfc;
364  unsigned int gate_ip_g3d;
365  unsigned int gate_ip_gen;
366  unsigned char res79[0xc];
367  unsigned int gate_ip_fsys;
368  unsigned char res80[0x4];
369  unsigned int gate_ip_gps;
370  unsigned int gate_ip_peric;
371  unsigned char res81[0xc];
372  unsigned int gate_ip_peris;
373  unsigned char res82[0x1c];
374  unsigned int gate_block;
375  unsigned char res83[0x7c];
376  unsigned int clkout_cmu_top;
377  unsigned int clkout_cmu_top_div_stat;
378  unsigned char res84[0x37f8];
379 
380  unsigned int src_lex; /* base + 0x14200 */
381  unsigned char res85[0x1fc];
382  unsigned int mux_stat_lex;
383  unsigned char res85b[0xfc];
384  unsigned int div_lex;
385  unsigned char res86[0xfc];
386  unsigned int div_stat_lex;
387  unsigned char res87[0x1fc];
388  unsigned int gate_ip_lex;
389  unsigned char res88[0x1fc];
390  unsigned int clkout_cmu_lex;
391  unsigned int clkout_cmu_lex_div_stat;
392  unsigned char res89[0x3af8];
393 
394  unsigned int div_r0x; /* base + 0x18500 */
395  unsigned char res90[0xfc];
396  unsigned int div_stat_r0x;
397  unsigned char res91[0x1fc];
398  unsigned int gate_ip_r0x;
399  unsigned char res92[0x1fc];
400  unsigned int clkout_cmu_r0x;
401  unsigned int clkout_cmu_r0x_div_stat;
402  unsigned char res94[0x3af8];
403 
404  unsigned int div_r1x; /* base + 0x1c500 */
405  unsigned char res95[0xfc];
406  unsigned int div_stat_r1x;
407  unsigned char res96[0x1fc];
408  unsigned int gate_ip_r1x;
409  unsigned char res97[0x1fc];
410  unsigned int clkout_cmu_r1x;
411  unsigned int clkout_cmu_r1x_div_stat;
412  unsigned char res98[0x3608];
413 
414  unsigned int bpll_lock; /* base + 0x20010 */
415  unsigned char res99[0xfc];
416  unsigned int bpll_con0;
417  unsigned int bpll_con1;
418  unsigned char res100[0xe8];
419  unsigned int src_cdrex;
420  unsigned char res101[0x1fc];
421  unsigned int mux_stat_cdrex;
422  unsigned char res102[0xfc];
423  unsigned int div_cdrex;
424  unsigned int div_cdrex2;
425  unsigned char res103[0xf8];
426  unsigned int div_stat_cdrex;
427  unsigned char res104[0x2fc];
428  unsigned int gate_ip_cdrex;
429  unsigned char res105[0xc];
430  unsigned int c2c_monitor;
431  unsigned int dmc_pwr_ctrl;
432  unsigned char res106[0x4];
433  unsigned int drex2_pause;
434  unsigned char res107[0xe0];
435  unsigned int clkout_cmu_cdrex;
436  unsigned int clkout_cmu_cdrex_div_stat;
437  unsigned char res108[0x8];
438  unsigned int lpddr3phy_ctrl;
439  unsigned char res109a[0xc];
440  unsigned int lpddr3phy_con3;
441  unsigned int pll_div2_sel;
442  unsigned char res109b[0xf5e4];
443 };
444 check_member(exynos5_clock, pll_div2_sel, 0x20a24);
445 
446 static struct exynos5_clock * const exynos_clock = (void *)EXYNOS5_CLOCK_BASE;
447 
448 struct exynos5_mct {
449  uint32_t mct_cfg;
450  uint8_t reserved0[0xfc];
451  uint32_t g_cnt_l;
452  uint32_t g_cnt_u;
453  uint8_t reserved1[0x8];
454  uint32_t g_cnt_wstat;
455  uint8_t reserved2[0xec];
456  uint32_t g_comp0_l;
457  uint32_t g_comp0_u;
458  uint32_t g_comp0_addr_incr;
459  uint8_t reserved3[0x4];
460  uint32_t g_comp1_l;
461  uint32_t g_comp1_u;
462  uint32_t g_comp1_addr_incr;
463  uint8_t reserved4[0x4];
464  uint32_t g_comp2_l;
465  uint32_t g_comp2_u;
466  uint32_t g_comp2_addr_incr;
467  uint8_t reserved5[0x4];
468  uint32_t g_comp3_l;
469  uint32_t g_comp3_u;
470  uint32_t g_comp3_addr_incr;
471  uint8_t reserved6[0x4];
472  uint32_t g_tcon;
473  uint32_t g_int_cstat;
474  uint32_t g_int_enb;
475  uint32_t g_wstat;
476  uint8_t reserved7[0xb0];
477  uint32_t l0_tcntb;
478  uint32_t l0_tcnto;
479  uint32_t l0_icntb;
480  uint32_t l0_icnto;
481  uint32_t l0_frcntb;
482  uint32_t l0_frcnto;
483  uint8_t reserved8[0x8];
484  uint32_t l0_tcon;
485  uint8_t reserved9[0xc];
486  uint32_t l0_int_cstat;
487  uint32_t l0_int_enb;
488  uint8_t reserved10[0x8];
489  uint32_t l0_wstat;
490  uint8_t reserved11[0xbc];
491  uint32_t l1_tcntb;
492  uint32_t l1_tcnto;
493  uint32_t l1_icntb;
494  uint32_t l1_icnto;
495  uint32_t l1_frcntb;
496  uint32_t l1_frcnto;
497  uint8_t reserved12[0x8];
498  uint32_t l1_tcon;
499  uint8_t reserved13[0xc];
500  uint32_t l1_int_cstat;
501  uint32_t l1_int_enb;
502  uint8_t reserved14[0x8];
503  uint32_t l1_wstat;
504 };
505 check_member(exynos5_mct, l1_wstat, 0x440);
506 
507 static struct exynos5_mct * const exynos_mct =
508  (void *)EXYNOS5_MULTI_CORE_TIMER_BASE;
509 
510 #define EXYNOS5_EPLLCON0_LOCKED_SHIFT 29 /* EPLL Locked bit position*/
511 #define EPLL_SRC_CLOCK 24000000 /*24 MHz Crystal Input */
512 #define TIMEOUT_EPLL_LOCK 1000
513 
514 #define AUDIO_0_RATIO_MASK 0x0f
515 #define AUDIO_1_RATIO_MASK 0x0f
516 
517 #define CLK_SRC_PERIC1 0x254
518 #define AUDIO1_SEL_MASK 0xf
519 #define CLK_SRC_AUDIOCDCLK1 0x0
520 #define CLK_SRC_XXTI 0x1
521 #define CLK_SRC_SCLK_EPLL 0x7
522 
523 /* CON0 bit-fields */
524 #define EPLL_CON0_MDIV_MASK 0x1ff
525 #define EPLL_CON0_PDIV_MASK 0x3f
526 #define EPLL_CON0_SDIV_MASK 0x7
527 #define EPLL_CON0_LOCKED_SHIFT 29
528 #define EPLL_CON0_MDIV_SHIFT 16
529 #define EPLL_CON0_PDIV_SHIFT 8
530 #define EPLL_CON0_SDIV_SHIFT 0
531 #define EPLL_CON0_LOCK_DET_EN_SHIFT 28
532 #define EPLL_CON0_LOCK_DET_EN_MASK 1
533 
534 /* structure for epll configuration used in audio clock configuration */
535 struct st_epll_con_val {
536  unsigned int freq_out; /* frequency out */
537  unsigned int en_lock_det; /* enable lock detect */
538  unsigned int m_div; /* m divider value */
539  unsigned int p_div; /* p divider value */
540  unsigned int s_div; /* s divider value */
541  unsigned int k_dsm; /* k value of delta signal modulator */
542 };
543 
544 /**
545  * Low-level function to set the clock pre-ratio for a peripheral
546  *
547  * @param periph_id Peripheral ID of peripheral to change
548  * @param divisor New divisor for this peripheral's clock
549  */
550 void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned int divisor);
551 
552 /**
553  * Low-level function to set the clock ratio for a peripheral
554  *
555  * @param periph_id Peripheral ID of peripheral to change
556  * @param divisor New divisor for this peripheral's clock
557  */
558 void clock_ll_set_ratio(enum periph_id periph_id, unsigned int divisor);
559 
560 /**
561  * Low-level function that selects the best clock scalars for a given rate and
562  * sets up the given peripheral's clock accordingly.
563  *
564  * @param periph_id Peripheral ID of peripheral to change
565  * @param rate Desired clock rate in Hz
566  *
567  * @return zero on success, negative on error
568  */
569 int clock_set_rate(enum periph_id periph_id, unsigned int rate);
570 
571 /* Clock gate unused IP */
572 void clock_gate(void);
573 
574 /* These are the ratio's for configuring ARM clock */
575 struct arm_clk_ratios {
576  unsigned int arm_freq_mhz; /* Frequency of ARM core in MHz */
577 
578  unsigned int apll_mdiv;
579  unsigned int apll_pdiv;
580  unsigned int apll_sdiv;
581 
582  unsigned int arm2_ratio;
583  unsigned int apll_ratio;
584  unsigned int pclk_dbg_ratio;
585  unsigned int atb_ratio;
586  unsigned int periph_ratio;
587  unsigned int acp_ratio;
588  unsigned int cpud_ratio;
589  unsigned int arm_ratio;
590 };
591 
592 /**
593  * Get the clock ratios for CPU configuration
594  *
595  * @return pointer to the clock ratios that we should use
596  */
597 struct arm_clk_ratios *get_arm_clk_ratios(void);
598 
599 /*
600  * Initialize clock for the device
601  */
602 struct mem_timings;
603 void system_clock_init(struct mem_timings *mem,
604  struct arm_clk_ratios *arm_clk_ratio);
605 
606 #endif
clock_ll_set_ratio
void clock_ll_set_ratio(enum periph_id periph_id, unsigned int divisor)
Low-level function to set the clock ratio for a peripheral.
Definition: clock.c:417
clock_ll_set_pre_ratio
void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned int divisor)
Low-level function to set the clock pre-ratio for a peripheral.
Definition: clock.c:374
get_pwm_clk
unsigned long get_pwm_clk(void)
get_arm_clk_ratios
struct arm_clk_ratios * get_arm_clk_ratios(void)
Get the clock ratios for CPU configuration.
Definition: clock.c:334
clock_gate
void clock_gate(void)
Definition: clock_init.c:267
clock_select_i2s_clk_source
void clock_select_i2s_clk_source(void)
Definition: clock.c:631
get_arm_clk
unsigned long get_arm_clk(void)
Definition: clock.c:315
clock_get_periph_rate
unsigned long clock_get_periph_rate(enum periph_id peripheral)
get the clk frequency of the required peripheral
Definition: clock.c:220
pll_src_bit
pll_src_bit
Definition: clk.h:20
SRC_VPLL
@ SRC_VPLL
Definition: clk.h:23
SRC_MPLL
@ SRC_MPLL
Definition: clk.h:21
SRC_EPLL
@ SRC_EPLL
Definition: clk.h:22
get_uart_clk
unsigned long get_uart_clk(int dev_index)
clock_set_i2s_clk_prescaler
int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq)
Definition: clock.c:637
clock_set_rate
int clock_set_rate(enum periph_id periph_id, unsigned int rate)
Low-level function that selects the best clock scalars for a given rate and sets up the given periphe...
Definition: clock.c:511
get_pll_clk
unsigned long get_pll_clk(int pllreg)
Definition: clock.c:156
exynos_mct
static struct exynos5_mct *const exynos_mct
Definition: clk.h:507
set_mmc_clk
void set_mmc_clk(int dev_index, unsigned int div)
Definition: clock.c:350
clock_set_mshci
int clock_set_mshci(enum periph_id peripheral)
Definition: clock.c:540
system_clock_init
void system_clock_init(struct mem_timings *mem, struct arm_clk_ratios *arm_clk_ratio)
Definition: clock_init.c:10
clock_epll_set_rate
int clock_epll_set_rate(unsigned long rate)
Definition: clock.c:577
exynos_clock
static struct exynos5_clock *const exynos_clock
Definition: clk.h:446
check_member
check_member(exynos5_clock, pll_div2_sel, 0x20a24)
periph_id
periph_id
Definition: periph.h:13
EXYNOS5_MULTI_CORE_TIMER_BASE
#define EXYNOS5_MULTI_CORE_TIMER_BASE
Definition: cpu.h:16
EXYNOS5_CLOCK_BASE
#define EXYNOS5_CLOCK_BASE
Definition: cpu.h:12
uint32_t
unsigned int uint32_t
Definition: stdint.h:14
s8
int8_t s8
Definition: stdint.h:44
uint8_t
unsigned char uint8_t
Definition: stdint.h:8
arm_clk_ratios
Definition: clk.h:575
arm_clk_ratios::arm_ratio
unsigned int arm_ratio
Definition: clk.h:589
arm_clk_ratios::atb_ratio
unsigned int atb_ratio
Definition: clk.h:585
arm_clk_ratios::cpud_ratio
unsigned int cpud_ratio
Definition: clk.h:588
arm_clk_ratios::arm2_ratio
unsigned int arm2_ratio
Definition: clk.h:582
arm_clk_ratios::apll_pdiv
unsigned int apll_pdiv
Definition: clk.h:579
arm_clk_ratios::periph_ratio
unsigned int periph_ratio
Definition: clk.h:586
arm_clk_ratios::acp_ratio
unsigned int acp_ratio
Definition: clk.h:587
arm_clk_ratios::apll_sdiv
unsigned int apll_sdiv
Definition: clk.h:580
arm_clk_ratios::pclk_dbg_ratio
unsigned int pclk_dbg_ratio
Definition: clk.h:584
arm_clk_ratios::apll_mdiv
unsigned int apll_mdiv
Definition: clk.h:578
arm_clk_ratios::arm_freq_mhz
unsigned int arm_freq_mhz
Definition: clk.h:576
arm_clk_ratios::apll_ratio
unsigned int apll_ratio
Definition: clk.h:583
clk_bit_info
Definition: clk.h:30
clk_bit_info::n_src_bits
s8 n_src_bits
Definition: clk.h:32
clk_bit_info::src_bit
s8 src_bit
Definition: clk.h:31
clk_bit_info::div_bit
s8 div_bit
Definition: clk.h:33
clk_bit_info::prediv_bit
s8 prediv_bit
Definition: clk.h:34
exynos5_clock
Definition: clk.h:88
exynos5_clock::res39
unsigned char res39[0xc]
Definition: clk.h:229
exynos5_clock::apll_con0_l5
unsigned int apll_con0_l5
Definition: clk.h:122
exynos5_clock::gate_ip_isp1
unsigned int gate_ip_isp1
Definition: clk.h:218
exynos5_clock::apll_con0_l3
unsigned int apll_con0_l3
Definition: clk.h:124
exynos5_clock::res65
unsigned char res65[0x8]
Definition: clk.h:321
exynos5_clock::res10
unsigned char res10[0x8]
Definition: clk.h:115
exynos5_clock::div_stat_top0
unsigned int div_stat_top0
Definition: clk.h:319
exynos5_clock::div_iem_l2
unsigned int div_iem_l2
Definition: clk.h:144
exynos5_clock::res19
unsigned char res19[0xf8]
Definition: clk.h:159
exynos5_clock::div_stat_disp0_1
unsigned int div_stat_disp0_1
Definition: clk.h:324
exynos5_clock::parityfail_status
unsigned int parityfail_status
Definition: clk.h:113
exynos5_clock::gate_top_sclk_gen
unsigned int gate_top_sclk_gen
Definition: clk.h:351
exynos5_clock::clkout_cmu_cpu_div_stat
unsigned int clkout_cmu_cpu_div_stat
Definition: clk.h:107
exynos5_clock::res4
unsigned char res4[0xfc]
Definition: clk.h:97
exynos5_clock::mux_stat_cpu
unsigned int mux_stat_cpu
Definition: clk.h:96
exynos5_clock::res71
unsigned char res71[0x8]
Definition: clk.h:346
exynos5_clock::res17
unsigned char res17[0xf8]
Definition: clk.h:155
exynos5_clock::gate_ip_gscl
unsigned int gate_ip_gscl
Definition: clk.h:360
exynos5_clock::res99
unsigned char res99[0xfc]
Definition: clk.h:415
exynos5_clock::gate_block
unsigned int gate_block
Definition: clk.h:374
exynos5_clock::res21
unsigned char res21[0x2f4]
Definition: clk.h:167
exynos5_clock::atclk_stopctrl
unsigned int atclk_stopctrl
Definition: clk.h:111
exynos5_clock::div_stat_peric5
unsigned int div_stat_peric5
Definition: clk.h:340
exynos5_clock::res48
unsigned char res48[0x18]
Definition: clk.h:265
exynos5_clock::src_mask_disp0_1
unsigned int src_mask_disp0_1
Definition: clk.h:272
exynos5_clock::gate_top_sclk_peric
unsigned int gate_top_sclk_peric
Definition: clk.h:356
exynos5_clock::gate_ip_gps
unsigned int gate_ip_gps
Definition: clk.h:369
exynos5_clock::src_mask_disp1_1
unsigned int src_mask_disp1_1
Definition: clk.h:274
exynos5_clock::res75
unsigned char res75[0xc]
Definition: clk.h:355
exynos5_clock::res31b
unsigned char res31b[0xc]
Definition: clk.h:198
exynos5_clock::div_stat_peric4
unsigned int div_stat_peric4
Definition: clk.h:339
exynos5_clock::gate_ip_gen
unsigned int gate_ip_gen
Definition: clk.h:365
exynos5_clock::div_iem_l4
unsigned int div_iem_l4
Definition: clk.h:142
exynos5_clock::res94
unsigned char res94[0x3af8]
Definition: clk.h:402
exynos5_clock::res68
unsigned char res68[0x4]
Definition: clk.h:329
exynos5_clock::div_stat_acp
unsigned int div_stat_acp
Definition: clk.h:193
exynos5_clock::res41a
unsigned char res41a[0xc]
Definition: clk.h:233
exynos5_clock::gpll_lock
unsigned int gpll_lock
Definition: clk.h:234
exynos5_clock::apll_con1_l4
unsigned int apll_con1_l4
Definition: clk.h:133
exynos5_clock::freq_cpu
unsigned int freq_cpu
Definition: clk.h:184
exynos5_clock::clkout_cmu_r0x_div_stat
unsigned int clkout_cmu_r0x_div_stat
Definition: clk.h:401
exynos5_clock::res97
unsigned char res97[0x1fc]
Definition: clk.h:409
exynos5_clock::gate_ip_disp0
unsigned int gate_ip_disp0
Definition: clk.h:361
exynos5_clock::dcgperf_map1
unsigned int dcgperf_map1
Definition: clk.h:180
exynos5_clock::div_stat_disp1_0
unsigned int div_stat_disp1_0
Definition: clk.h:325
exynos5_clock::drex2_pause
unsigned int drex2_pause
Definition: clk.h:433
exynos5_clock::res18
unsigned char res18[0x100]
Definition: clk.h:157
exynos5_clock::bpll_con0
unsigned int bpll_con0
Definition: clk.h:416
exynos5_clock::src_cpu
unsigned int src_cpu
Definition: clk.h:94
exynos5_clock::gate_ip_peric
unsigned int gate_ip_peric
Definition: clk.h:370
exynos5_clock::vpll_lock
unsigned int vpll_lock
Definition: clk.h:232
exynos5_clock::gate_ip_g3d
unsigned int gate_ip_g3d
Definition: clk.h:364
exynos5_clock::res80
unsigned char res80[0x4]
Definition: clk.h:368
exynos5_clock::bpll_con1
unsigned int bpll_con1
Definition: clk.h:417
exynos5_clock::res83
unsigned char res83[0x7c]
Definition: clk.h:375
exynos5_clock::gate_ip_cdrex
unsigned int gate_ip_cdrex
Definition: clk.h:428
exynos5_clock::gate_ip_core
unsigned int gate_ip_core
Definition: clk.h:168
exynos5_clock::apll_con1_l6
unsigned int apll_con1_l6
Definition: clk.h:131
exynos5_clock::epll_con2
unsigned int epll_con2
Definition: clk.h:241
exynos5_clock::div_stat_peric2
unsigned int div_stat_peric2
Definition: clk.h:337
exynos5_clock::div2_stat1
unsigned int div2_stat1
Definition: clk.h:345
exynos5_clock::div_stat_r0x
unsigned int div_stat_r0x
Definition: clk.h:396
exynos5_clock::gpll_con1
unsigned int gpll_con1
Definition: clk.h:248
exynos5_clock::res61
unsigned char res61[0x10]
Definition: clk.h:311
exynos5_clock::res47
unsigned char res47[0x8]
Definition: clk.h:262
exynos5_clock::res98
unsigned char res98[0x3608]
Definition: clk.h:412
exynos5_clock::div_peric5
unsigned int div_peric5
Definition: clk.h:310
exynos5_clock::res57
unsigned char res57[0x8]
Definition: clk.h:291
exynos5_clock::res69
unsigned char res69[0x10]
Definition: clk.h:341
exynos5_clock::res34
unsigned char res34[0x3f4]
Definition: clk.h:215
exynos5_clock::src_mask_gscl
unsigned int src_mask_gscl
Definition: clk.h:270
exynos5_clock::res62
unsigned char res62[0xc]
Definition: clk.h:313
exynos5_clock::parityfail_clear
unsigned int parityfail_clear
Definition: clk.h:114
exynos5_clock::sclk_div_isp
unsigned int sclk_div_isp
Definition: clk.h:312
exynos5_clock::clkout_cmu_cpu
unsigned int clkout_cmu_cpu
Definition: clk.h:106
exynos5_clock::gate_ip_fsys
unsigned int gate_ip_fsys
Definition: clk.h:367
exynos5_clock::freq_dpm
unsigned int freq_dpm
Definition: clk.h:185
exynos5_clock::src_disp0_1
unsigned int src_disp0_1
Definition: clk.h:256
exynos5_clock::div_stat_isp1
unsigned int div_stat_isp1
Definition: clk.h:213
exynos5_clock::res55
unsigned char res55[0x9c]
Definition: clk.h:283
exynos5_clock::res38
unsigned char res38[0x3618]
Definition: clk.h:226
exynos5_clock::div_disp1_1
unsigned int div_disp1_1
Definition: clk.h:296
exynos5_clock::div_stat_gscl
unsigned int div_stat_gscl
Definition: clk.h:322
exynos5_clock::mux_stat_cdrex
unsigned int mux_stat_cdrex
Definition: clk.h:421
exynos5_clock::res49
unsigned char res49[0x9c]
Definition: clk.h:267
exynos5_clock::apll_con0_l7
unsigned int apll_con0_l7
Definition: clk.h:120
exynos5_clock::res13
unsigned char res13[0xe0]
Definition: clk.h:137
exynos5_clock::div_stat_fsys0
unsigned int div_stat_fsys0
Definition: clk.h:331
exynos5_clock::sclk_div_stat_isp
unsigned int sclk_div_stat_isp
Definition: clk.h:342
exynos5_clock::res77
unsigned char res77[0xac]
Definition: clk.h:359
exynos5_clock::res20
unsigned char res20[0xf4]
Definition: clk.h:163
exynos5_clock::div_peric1
unsigned int div_peric1
Definition: clk.h:306
exynos5_clock::src_top2
unsigned int src_top2
Definition: clk.h:252
exynos5_clock::res79
unsigned char res79[0xc]
Definition: clk.h:366
exynos5_clock::gate_sclk_cpu
unsigned int gate_sclk_cpu
Definition: clk.h:104
exynos5_clock::div_top0
unsigned int div_top0
Definition: clk.h:289
exynos5_clock::res15
unsigned char res15[0xfc]
Definition: clk.h:149
exynos5_clock::iem_control
unsigned int iem_control
Definition: clk.h:127
exynos5_clock::div_stat_isp0
unsigned int div_stat_isp0
Definition: clk.h:212
exynos5_clock::apll_con0_l4
unsigned int apll_con0_l4
Definition: clk.h:123
exynos5_clock::res14
unsigned char res14[0x2ce0]
Definition: clk.h:146
exynos5_clock::src_disp1_0
unsigned int src_disp1_0
Definition: clk.h:257
exynos5_clock::clkout_cmu_core_div_stat
unsigned int clkout_cmu_core_div_stat
Definition: clk.h:172
exynos5_clock::gate_sclk_isp
unsigned int gate_sclk_isp
Definition: clk.h:220
exynos5_clock::div_stat_peric0
unsigned int div_stat_peric0
Definition: clk.h:335
exynos5_clock::res95
unsigned char res95[0xfc]
Definition: clk.h:405
exynos5_clock::sclk_src_isp
unsigned int sclk_src_isp
Definition: clk.h:266
exynos5_clock::res106
unsigned char res106[0x4]
Definition: clk.h:432
exynos5_clock::res64
unsigned char res64[0x6c]
Definition: clk.h:318
exynos5_clock::apll_con1_l1
unsigned int apll_con1_l1
Definition: clk.h:136
exynos5_clock::apll_con0_l6
unsigned int apll_con0_l6
Definition: clk.h:121
exynos5_clock::clkout_cmu_acp_div_stat
unsigned int clkout_cmu_acp_div_stat
Definition: clk.h:204
exynos5_clock::clkout_cmu_r1x
unsigned int clkout_cmu_r1x
Definition: clk.h:410
exynos5_clock::src_mask_isp
unsigned int src_mask_isp
Definition: clk.h:282
exynos5_clock::src_top0
unsigned int src_top0
Definition: clk.h:250
exynos5_clock::div_fsys0
unsigned int div_fsys0
Definition: clk.h:301
exynos5_clock::div_cdrex
unsigned int div_cdrex
Definition: clk.h:423
exynos5_clock::apll_con1
unsigned int apll_con1
Definition: clk.h:92
exynos5_clock::res8
unsigned char res8[0x5f8]
Definition: clk.h:108
exynos5_clock::res96
unsigned char res96[0x1fc]
Definition: clk.h:407
exynos5_clock::res2
unsigned char res2[0xf8]
Definition: clk.h:93
exynos5_clock::cpll_con0
unsigned int cpll_con0
Definition: clk.h:236
exynos5_clock::clkout_cmu_core
unsigned int clkout_cmu_core
Definition: clk.h:171
exynos5_clock::res5
unsigned char res5[0xf8]
Definition: clk.h:100
exynos5_clock::div_fsys2
unsigned int div_fsys2
Definition: clk.h:303
exynos5_clock::mux_stat_core1
unsigned int mux_stat_core1
Definition: clk.h:158
exynos5_clock::src_peric1
unsigned int src_peric1
Definition: clk.h:264
exynos5_clock::div_disp0_1
unsigned int div_disp0_1
Definition: clk.h:294
exynos5_clock::res85
unsigned char res85[0x1fc]
Definition: clk.h:381
exynos5_clock::res12
unsigned char res12[0xdc]
Definition: clk.h:128
exynos5_clock::div_core0
unsigned int div_core0
Definition: clk.h:160
exynos5_clock::div_fsys1
unsigned int div_fsys1
Definition: clk.h:302
exynos5_clock::vpll_con0
unsigned int vpll_con0
Definition: clk.h:243
exynos5_clock::gate_ip_mfc
unsigned int gate_ip_mfc
Definition: clk.h:363
exynos5_clock::src_gscl
unsigned int src_gscl
Definition: clk.h:254
exynos5_clock::res41b
unsigned char res41b[0xcc]
Definition: clk.h:235
exynos5_clock::res86
unsigned char res86[0xfc]
Definition: clk.h:385
exynos5_clock::res56
unsigned char res56[0xf0]
Definition: clk.h:288
exynos5_clock::res44a
unsigned char res44a[0x4]
Definition: clk.h:246
exynos5_clock::div_acp
unsigned int div_acp
Definition: clk.h:191
exynos5_clock::div_peric3
unsigned int div_peric3
Definition: clk.h:308
exynos5_clock::gate_ip_peris
unsigned int gate_ip_peris
Definition: clk.h:372
exynos5_clock::div_syslft
unsigned int div_syslft
Definition: clk.h:197
exynos5_clock::apll_con1_l3
unsigned int apll_con1_l3
Definition: clk.h:134
exynos5_clock::div_stat_peric3
unsigned int div_stat_peric3
Definition: clk.h:338
exynos5_clock::mux_stat_top2
unsigned int mux_stat_top2
Definition: clk.h:286
exynos5_clock::div_top1
unsigned int div_top1
Definition: clk.h:290
exynos5_clock::res31c
unsigned char res31c[0xc]
Definition: clk.h:200
exynos5_clock::res109b
unsigned char res109b[0xf5e4]
Definition: clk.h:442
exynos5_clock::clkout_cmu_lex_div_stat
unsigned int clkout_cmu_lex_div_stat
Definition: clk.h:391
exynos5_clock::res92
unsigned char res92[0x1fc]
Definition: clk.h:399
exynos5_clock::dcgidx_map1
unsigned int dcgidx_map1
Definition: clk.h:176
exynos5_clock::div_fsys3
unsigned int div_fsys3
Definition: clk.h:304
exynos5_clock::div_disp1_0
unsigned int div_disp1_0
Definition: clk.h:295
exynos5_clock::src_disp0_0
unsigned int src_disp0_0
Definition: clk.h:255
exynos5_clock::res81
unsigned char res81[0xc]
Definition: clk.h:371
exynos5_clock::div_stat_r1x
unsigned int div_stat_r1x
Definition: clk.h:406
exynos5_clock::apll_con0_l1
unsigned int apll_con0_l1
Definition: clk.h:126
exynos5_clock::src_mau
unsigned int src_mau
Definition: clk.h:260
exynos5_clock::div4_stat
unsigned int div4_stat
Definition: clk.h:347
exynos5_clock::vpll_con2
unsigned int vpll_con2
Definition: clk.h:245
exynos5_clock::mpll_lock
unsigned int mpll_lock
Definition: clk.h:148
exynos5_clock::src_mask_maudio
unsigned int src_mask_maudio
Definition: clk.h:275
exynos5_clock::dcgperf_map0
unsigned int dcgperf_map0
Definition: clk.h:179
exynos5_clock::res105
unsigned char res105[0xc]
Definition: clk.h:429
exynos5_clock::res7
unsigned char res7[0x1fc]
Definition: clk.h:105
exynos5_clock::res42
unsigned char res42[0x8]
Definition: clk.h:238
exynos5_clock::gate_ip_r0x
unsigned int gate_ip_r0x
Definition: clk.h:398
exynos5_clock::gate_top_sclk_isp
unsigned int gate_top_sclk_isp
Definition: clk.h:358
exynos5_clock::c2c_monitor
unsigned int c2c_monitor
Definition: clk.h:430
exynos5_clock::src_core0
unsigned int src_core0
Definition: clk.h:153
exynos5_clock::res30
unsigned char res30[0x1fc]
Definition: clk.h:194
exynos5_clock::res63
unsigned char res63[0x8]
Definition: clk.h:316
exynos5_clock::src_fsys
unsigned int src_fsys
Definition: clk.h:261
exynos5_clock::src_core1
unsigned int src_core1
Definition: clk.h:154
exynos5_clock::epll_con1
unsigned int epll_con1
Definition: clk.h:240
exynos5_clock::apll_lock
unsigned int apll_lock
Definition: clk.h:89
exynos5_clock::div_iem_l3
unsigned int div_iem_l3
Definition: clk.h:143
exynos5_clock::dmc_pwr_ctrl
unsigned int dmc_pwr_ctrl
Definition: clk.h:431
exynos5_clock::div_iem_l7
unsigned int div_iem_l7
Definition: clk.h:139
exynos5_clock::res16
unsigned char res16[0xf8]
Definition: clk.h:152
exynos5_clock::div_stat_gen
unsigned int div_stat_gen
Definition: clk.h:328
exynos5_clock::res29
unsigned char res29[0xfc]
Definition: clk.h:192
exynos5_clock::res109a
unsigned char res109a[0xc]
Definition: clk.h:439
exynos5_clock::div_iem_l8
unsigned int div_iem_l8
Definition: clk.h:138
exynos5_clock::res11
unsigned char res11[0xd8]
Definition: clk.h:118
exynos5_clock::dvcidx_map
unsigned int dvcidx_map
Definition: clk.h:182
exynos5_clock::div_lex
unsigned int div_lex
Definition: clk.h:384
exynos5_clock::res22
unsigned char res22[0xf8]
Definition: clk.h:170
exynos5_clock::div_iem_l1
unsigned int div_iem_l1
Definition: clk.h:145
exynos5_clock::res101
unsigned char res101[0x1fc]
Definition: clk.h:420
exynos5_clock::src_mask_disp0_0
unsigned int src_mask_disp0_0
Definition: clk.h:271
exynos5_clock::gate_top_sclk_disp1
unsigned int gate_top_sclk_disp1
Definition: clk.h:350
exynos5_clock::pwr_ctr2
unsigned int pwr_ctr2
Definition: clk.h:117
exynos5_clock::res59
unsigned char res59[0x8]
Definition: clk.h:297
exynos5_clock::gate_ip_isp0
unsigned int gate_ip_isp0
Definition: clk.h:217
exynos5_clock::src_mask_peric0
unsigned int src_mask_peric0
Definition: clk.h:279
exynos5_clock::div_isp0
unsigned int div_isp0
Definition: clk.h:207
exynos5_clock::div2_ratio0
unsigned int div2_ratio0
Definition: clk.h:314
exynos5_clock::gate_ip_acp
unsigned int gate_ip_acp
Definition: clk.h:195
exynos5_clock::div_isp2
unsigned int div_isp2
Definition: clk.h:209
exynos5_clock::res31d
unsigned char res31d[0xdc]
Definition: clk.h:202
exynos5_clock::div_stat_cpu0
unsigned int div_stat_cpu0
Definition: clk.h:101
exynos5_clock::gate_top_sclk_mau
unsigned int gate_top_sclk_mau
Definition: clk.h:353
exynos5_clock::res74
unsigned char res74[0xc]
Definition: clk.h:352
exynos5_clock::div_iem_l6
unsigned int div_iem_l6
Definition: clk.h:140
exynos5_clock::mpll_con1
unsigned int mpll_con1
Definition: clk.h:151
exynos5_clock::res54
unsigned char res54[0x18]
Definition: clk.h:281
exynos5_clock::cpll_lock
unsigned int cpll_lock
Definition: clk.h:228
exynos5_clock::div_sysrgt
unsigned int div_sysrgt
Definition: clk.h:162
exynos5_clock::div_stat_syslft
unsigned int div_stat_syslft
Definition: clk.h:199
exynos5_clock::gate_ip_lex
unsigned int gate_ip_lex
Definition: clk.h:388
exynos5_clock::div_r1x
unsigned int div_r1x
Definition: clk.h:404
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Definition: clk.h:196
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unsigned int clkout_cmu_top_div_stat
Definition: clk.h:377
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Definition: clk.h:438
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Definition: clk.h:373
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Definition: clk.h:348
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unsigned int div4_ratio
Definition: clk.h:317
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Definition: clk.h:156
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Definition: clk.h:95
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Definition: clk.h:386
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Definition: clk.h:188
exynos5_clock::div_disp0_0
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Definition: clk.h:293
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unsigned int div_cpu1
Definition: clk.h:99
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unsigned int mcuisp_pwr_ctrl
Definition: clk.h:222
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unsigned int clkout_cmu_cdrex
Definition: clk.h:435
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Definition: clk.h:116
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Definition: clk.h:119
exynos5_clock::res37
unsigned char res37[0xec]
Definition: clk.h:223
exynos5_clock::gate_top_sclk_disp0
unsigned int gate_top_sclk_disp0
Definition: clk.h:349
exynos5_clock::epll_lock
unsigned int epll_lock
Definition: clk.h:230
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unsigned int clkout_cmu_isp_div_stat
Definition: clk.h:225
exynos5_clock::src_top1
unsigned int src_top1
Definition: clk.h:251
exynos5_clock::src_mask_disp1_0
unsigned int src_mask_disp1_0
Definition: clk.h:273
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Definition: clk.h:249
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Definition: clk.h:397
exynos5_clock::res107
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Definition: clk.h:434
exynos5_clock::res100
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Definition: clk.h:418
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Definition: clk.h:231
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unsigned int clkout_cmu_top
Definition: clk.h:376
exynos5_clock::src_mask_top
unsigned int src_mask_top
Definition: clk.h:268
exynos5_clock::res50
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Definition: clk.h:269
exynos5_clock::res24
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Definition: clk.h:178
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Definition: clk.h:327
exynos5_clock::src_mask_peric1
unsigned int src_mask_peric1
Definition: clk.h:280
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Definition: clk.h:378
exynos5_clock::res33
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Definition: clk.h:210
exynos5_clock::res70
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Definition: clk.h:343
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unsigned int mux_stat_top0
Definition: clk.h:284
exynos5_clock::div_stat_maudio
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Definition: clk.h:330
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Definition: clk.h:177
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Definition: clk.h:208
exynos5_clock::src_cdrex
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Definition: clk.h:419
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Definition: clk.h:132
exynos5_clock::res35
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Definition: clk.h:219
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Definition: clk.h:112
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Definition: clk.h:90
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Definition: clk.h:237
exynos5_clock::res90
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Definition: clk.h:395
exynos5_clock::div_stat_top1
unsigned int div_stat_top1
Definition: clk.h:320
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Definition: clk.h:173
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unsigned int src_lex
Definition: clk.h:380
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unsigned int apll_con0_l2
Definition: clk.h:125
exynos5_clock::clkout_cmu_lex
unsigned int clkout_cmu_lex
Definition: clk.h:390
exynos5_clock::div_stat_fsys3
unsigned int div_stat_fsys3
Definition: clk.h:334
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unsigned int div_cdrex2
Definition: clk.h:424
exynos5_clock::div_stat_isp2
unsigned int div_stat_isp2
Definition: clk.h:214
exynos5_clock::div_peric2
unsigned int div_peric2
Definition: clk.h:307
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Definition: clk.h:427
exynos5_clock::lpddr3phy_con3
unsigned int lpddr3phy_con3
Definition: clk.h:440
exynos5_clock::div_mau
unsigned int div_mau
Definition: clk.h:300
exynos5_clock::div_stat_peric1
unsigned int div_stat_peric1
Definition: clk.h:336
exynos5_clock::armclk_stopctrl
unsigned int armclk_stopctrl
Definition: clk.h:110
exynos5_clock::apll_con1_l2
unsigned int apll_con1_l2
Definition: clk.h:135
exynos5_clock::res102
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Definition: clk.h:422
exynos5_clock::src_disp1_1
unsigned int src_disp1_1
Definition: clk.h:258
exynos5_clock::div_stat_fsys1
unsigned int div_stat_fsys1
Definition: clk.h:332
exynos5_clock::gate_top_sclk_fsys
unsigned int gate_top_sclk_fsys
Definition: clk.h:354
exynos5_clock::res52
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Definition: clk.h:276
exynos5_clock::gate_ip_sysrgt
unsigned int gate_ip_sysrgt
Definition: clk.h:169
exynos5_clock::gate_ip_r1x
unsigned int gate_ip_r1x
Definition: clk.h:408
exynos5_clock::res6
unsigned char res6[0x1f8]
Definition: clk.h:103
exynos5_clock::bpll_lock
unsigned int bpll_lock
Definition: clk.h:414
exynos5_clock::res108
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Definition: clk.h:437
exynos5_clock::gate_ip_disp1
unsigned int gate_ip_disp1
Definition: clk.h:362
exynos5_clock::epll_con0
unsigned int epll_con0
Definition: clk.h:239
exynos5_clock::apll_con1_l7
unsigned int apll_con1_l7
Definition: clk.h:130
exynos5_clock::apll_con1_l8
unsigned int apll_con1_l8
Definition: clk.h:129
exynos5_clock::div_stat_disp0_0
unsigned int div_stat_disp0_0
Definition: clk.h:323
exynos5_clock::apll_con0
unsigned int apll_con0
Definition: clk.h:91
exynos5_clock::clkout_cmu_cdrex_div_stat
unsigned int clkout_cmu_cdrex_div_stat
Definition: clk.h:436
exynos5_clock::div_stat_sysrgt
unsigned int div_stat_sysrgt
Definition: clk.h:166
exynos5_clock::clkout_cmu_r1x_div_stat
unsigned int clkout_cmu_r1x_div_stat
Definition: clk.h:411
exynos5_clock::res53
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Definition: clk.h:278
exynos5_clock::src_top3
unsigned int src_top3
Definition: clk.h:253
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Definition: clk.h:299
exynos5_clock::res89
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Definition: clk.h:392
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unsigned int div_cpu0
Definition: clk.h:98
exynos5_clock::res85b
unsigned char res85b[0xfc]
Definition: clk.h:383
exynos5_clock::res88
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Definition: clk.h:389
exynos5_clock::res36
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Definition: clk.h:221
exynos5_clock::gate_bus_syslft
unsigned int gate_bus_syslft
Definition: clk.h:201
exynos5_clock::mux_stat_lex
unsigned int mux_stat_lex
Definition: clk.h:382
exynos5_clock::dvsemclk_en
unsigned int dvsemclk_en
Definition: clk.h:187
exynos5_clock::res25
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Definition: clk.h:181
exynos5_clock::src_mask_fsys
unsigned int src_mask_fsys
Definition: clk.h:277
exynos5_clock::res32
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Definition: clk.h:205
exynos5_clock::div2_stat0
unsigned int div2_stat0
Definition: clk.h:344
exynos5_clock::mpll_con0
unsigned int mpll_con0
Definition: clk.h:150
exynos5_clock::div_stat_cpu1
unsigned int div_stat_cpu1
Definition: clk.h:102
exynos5_clock::div_peric0
unsigned int div_peric0
Definition: clk.h:305
exynos5_clock::clkout_cmu_acp
unsigned int clkout_cmu_acp
Definition: clk.h:203
exynos5_clock::clkout_cmu_r0x
unsigned int clkout_cmu_r0x
Definition: clk.h:400
exynos5_clock::res76
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Definition: clk.h:357
exynos5_clock::vpll_con1
unsigned int vpll_con1
Definition: clk.h:244
exynos5_clock::res46
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Definition: clk.h:259
exynos5_clock::div_stat_disp1_1
unsigned int div_stat_disp1_1
Definition: clk.h:326
exynos5_clock::mux_stat_top3
unsigned int mux_stat_top3
Definition: clk.h:287
exynos5_clock::res26
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Definition: clk.h:183
exynos5_clock::div_r0x
unsigned int div_r0x
Definition: clk.h:394
exynos5_clock::mux_stat_top1
unsigned int mux_stat_top1
Definition: clk.h:285
exynos5_clock::gpll_con0
unsigned int gpll_con0
Definition: clk.h:247
exynos5_clock::div_gscl
unsigned int div_gscl
Definition: clk.h:292
exynos5_clock::div_stat_fsys2
unsigned int div_stat_fsys2
Definition: clk.h:333
exynos5_clock::div_peric4
unsigned int div_peric4
Definition: clk.h:309
exynos5_clock::div_gen
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Definition: clk.h:298
exynos5_clock::div2_ratio1
unsigned int div2_ratio1
Definition: clk.h:315
exynos5_clock::div_stat_core0
unsigned int div_stat_core0
Definition: clk.h:164
exynos5_clock::div_stat_cdrex
unsigned int div_stat_cdrex
Definition: clk.h:426
exynos5_clock::div_iem_l5
unsigned int div_iem_l5
Definition: clk.h:141
exynos5_clock::src_peric0
unsigned int src_peric0
Definition: clk.h:263
exynos5_clock::pll_div2_sel
unsigned int pll_div2_sel
Definition: clk.h:441
exynos5_clock::res103
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Definition: clk.h:425
exynos5_clock::div_core1
unsigned int div_core1
Definition: clk.h:161
exynos5_clock::res27
unsigned char res27[0x18]
Definition: clk.h:186
exynos5_clock::div_stat_core1
unsigned int div_stat_core1
Definition: clk.h:165
exynos5_clock::dcgidx_map0
unsigned int dcgidx_map0
Definition: clk.h:175
exynos5_clock::res87
unsigned char res87[0x1fc]
Definition: clk.h:387
exynos5_clock::clkout_cmu_isp
unsigned int clkout_cmu_isp
Definition: clk.h:224
exynos5_clock::res43
unsigned char res43[0x4]
Definition: clk.h:242
exynos5_clock::res28
unsigned char res28[0x3478]
Definition: clk.h:189
exynos5_mct
Definition: clk.h:448
exynos5_mct::reserved7
uint8_t reserved7[0xb0]
Definition: clk.h:476
exynos5_mct::l0_frcntb
uint32_t l0_frcntb
Definition: clk.h:481
exynos5_mct::g_cnt_wstat
uint32_t g_cnt_wstat
Definition: clk.h:454
exynos5_mct::g_int_enb
uint32_t g_int_enb
Definition: clk.h:474
exynos5_mct::l0_tcntb
uint32_t l0_tcntb
Definition: clk.h:477
exynos5_mct::reserved8
uint8_t reserved8[0x8]
Definition: clk.h:483
exynos5_mct::reserved4
uint8_t reserved4[0x4]
Definition: clk.h:463
exynos5_mct::g_wstat
uint32_t g_wstat
Definition: clk.h:475
exynos5_mct::g_comp0_l
uint32_t g_comp0_l
Definition: clk.h:456
exynos5_mct::l1_tcntb
uint32_t l1_tcntb
Definition: clk.h:491
exynos5_mct::reserved12
uint8_t reserved12[0x8]
Definition: clk.h:497
exynos5_mct::l0_tcnto
uint32_t l0_tcnto
Definition: clk.h:478
exynos5_mct::l1_frcntb
uint32_t l1_frcntb
Definition: clk.h:495
exynos5_mct::reserved2
uint8_t reserved2[0xec]
Definition: clk.h:455
exynos5_mct::reserved14
uint8_t reserved14[0x8]
Definition: clk.h:502
exynos5_mct::mct_cfg
uint32_t mct_cfg
Definition: clk.h:449
exynos5_mct::reserved1
uint8_t reserved1[0x8]
Definition: clk.h:453
exynos5_mct::reserved9
uint8_t reserved9[0xc]
Definition: clk.h:485
exynos5_mct::reserved13
uint8_t reserved13[0xc]
Definition: clk.h:499
exynos5_mct::l0_frcnto
uint32_t l0_frcnto
Definition: clk.h:482
exynos5_mct::reserved11
uint8_t reserved11[0xbc]
Definition: clk.h:490
exynos5_mct::l0_int_enb
uint32_t l0_int_enb
Definition: clk.h:487
exynos5_mct::l1_icntb
uint32_t l1_icntb
Definition: clk.h:493
exynos5_mct::l0_int_cstat
uint32_t l0_int_cstat
Definition: clk.h:486
exynos5_mct::g_comp0_addr_incr
uint32_t g_comp0_addr_incr
Definition: clk.h:458
exynos5_mct::g_comp1_addr_incr
uint32_t g_comp1_addr_incr
Definition: clk.h:462
exynos5_mct::g_tcon
uint32_t g_tcon
Definition: clk.h:472
exynos5_mct::g_int_cstat
uint32_t g_int_cstat
Definition: clk.h:473
exynos5_mct::reserved10
uint8_t reserved10[0x8]
Definition: clk.h:488
exynos5_mct::reserved0
uint8_t reserved0[0xfc]
Definition: clk.h:450
exynos5_mct::l1_wstat
uint32_t l1_wstat
Definition: clk.h:503
exynos5_mct::g_comp0_u
uint32_t g_comp0_u
Definition: clk.h:457
exynos5_mct::l1_icnto
uint32_t l1_icnto
Definition: clk.h:494
exynos5_mct::l0_tcon
uint32_t l0_tcon
Definition: clk.h:484
exynos5_mct::g_comp2_addr_incr
uint32_t g_comp2_addr_incr
Definition: clk.h:466
exynos5_mct::l1_tcon
uint32_t l1_tcon
Definition: clk.h:498
exynos5_mct::l0_icntb
uint32_t l0_icntb
Definition: clk.h:479
exynos5_mct::g_comp1_l
uint32_t g_comp1_l
Definition: clk.h:460
exynos5_mct::l1_int_enb
uint32_t l1_int_enb
Definition: clk.h:501
exynos5_mct::g_cnt_l
uint32_t g_cnt_l
Definition: clk.h:451
exynos5_mct::g_comp3_addr_incr
uint32_t g_comp3_addr_incr
Definition: clk.h:470
exynos5_mct::l1_frcnto
uint32_t l1_frcnto
Definition: clk.h:496
exynos5_mct::reserved5
uint8_t reserved5[0x4]
Definition: clk.h:467
exynos5_mct::l1_int_cstat
uint32_t l1_int_cstat
Definition: clk.h:500
exynos5_mct::g_cnt_u
uint32_t g_cnt_u
Definition: clk.h:452
exynos5_mct::g_comp3_u
uint32_t g_comp3_u
Definition: clk.h:469
exynos5_mct::g_comp2_l
uint32_t g_comp2_l
Definition: clk.h:464
exynos5_mct::l0_icnto
uint32_t l0_icnto
Definition: clk.h:480
exynos5_mct::g_comp2_u
uint32_t g_comp2_u
Definition: clk.h:465
exynos5_mct::g_comp3_l
uint32_t g_comp3_l
Definition: clk.h:468
exynos5_mct::reserved3
uint8_t reserved3[0x4]
Definition: clk.h:459
exynos5_mct::reserved6
uint8_t reserved6[0x4]
Definition: clk.h:471
exynos5_mct::l1_tcnto
uint32_t l1_tcnto
Definition: clk.h:492
exynos5_mct::g_comp1_u
uint32_t g_comp1_u
Definition: clk.h:461
exynos5_mct::l0_wstat
uint32_t l0_wstat
Definition: clk.h:489
mem_timings
Definition: dmc.h:246
rate
Definition: pll.c:262
st_epll_con_val
Definition: clk.h:535
st_epll_con_val::en_lock_det
unsigned int en_lock_det
Definition: clk.h:537
st_epll_con_val::m_div
unsigned int m_div
Definition: clk.h:538
st_epll_con_val::s_div
unsigned int s_div
Definition: clk.h:540
st_epll_con_val::k_dsm
unsigned int k_dsm
Definition: clk.h:541
st_epll_con_val::p_div
unsigned int p_div
Definition: clk.h:539
st_epll_con_val::freq_out
unsigned int freq_out
Definition: clk.h:536