5 #ifndef CPU_SAMSUNG_EXYNOS5250_SETUP_H
6 #define CPU_SAMSUNG_EXYNOS5250_SETUP_H
13 #define TZPC0_BASE 0x10100000
14 #define TZPC1_BASE 0x10110000
15 #define TZPC2_BASE 0x10120000
16 #define TZPC3_BASE 0x10130000
17 #define TZPC4_BASE 0x10140000
18 #define TZPC5_BASE 0x10150000
19 #define TZPC6_BASE 0x10160000
20 #define TZPC7_BASE 0x10170000
21 #define TZPC8_BASE 0x10180000
22 #define TZPC9_BASE 0x10190000
24 #define APLL_FOUT (1 << 0)
27 #define APLL_CON1_VAL (0x00203800)
30 #define MPLL_CON1_VAL (0x00203800)
33 #define CPLL_CON1_VAL (0x00203800)
36 #define GPLL_CON1_VAL (0x00203800)
39 #define EPLL_CON1_VAL 0x00000000
40 #define EPLL_CON2_VAL 0x00000080
43 #define VPLL_CON1_VAL 0x00000000
44 #define VPLL_CON2_VAL 0x00000080
47 #define BPLL_CON1_VAL 0x00203800
50 #define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
56 #define MUX_APLL_SEL 1
58 #define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
59 | (MUX_CPU_SEL << 16) \
63 #define DMC_MEMCONTROL_CLK_STOP_DISABLE (0 << 0)
64 #define DMC_MEMCONTROL_DPWRDN_DISABLE (0 << 1)
65 #define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE (0 << 2)
66 #define DMC_MEMCONTROL_TP_DISABLE (0 << 4)
67 #define DMC_MEMCONTROL_DSREF_DISABLE (0 << 5)
68 #define DMC_MEMCONTROL_DSREF_ENABLE (1 << 5)
69 #define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6)
71 #define DMC_MEMCONTROL_MEM_TYPE_LPDDR3 (7 << 8)
72 #define DMC_MEMCONTROL_MEM_TYPE_DDR3 (6 << 8)
73 #define DMC_MEMCONTROL_MEM_TYPE_LPDDR2 (5 << 8)
75 #define DMC_MEMCONTROL_MEM_WIDTH_32BIT (2 << 12)
77 #define DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16)
78 #define DMC_MEMCONTROL_NUM_CHIP_2 (1 << 16)
80 #define DMC_MEMCONTROL_BL_8 (3 << 20)
81 #define DMC_MEMCONTROL_BL_4 (2 << 20)
83 #define DMC_MEMCONTROL_PZQ_DISABLE (0 << 24)
85 #define DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25)
86 #define DMC_MEMCONTROL_MRR_BYTE_15_8 (1 << 25)
87 #define DMC_MEMCONTROL_MRR_BYTE_23_16 (2 << 25)
88 #define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25)
91 #define DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED (1 << 12)
92 #define DMC_MEMCONFIGx_CHIP_COL_10 (3 << 8)
93 #define DMC_MEMCONFIGx_CHIP_ROW_14 (2 << 4)
94 #define DMC_MEMCONFIGx_CHIP_ROW_15 (3 << 4)
95 #define DMC_MEMCONFIGx_CHIP_BANK_8 (3 << 0)
97 #define DMC_MEMBASECONFIGx_CHIP_BASE(x) (x << 16)
98 #define DMC_MEMBASECONFIGx_CHIP_MASK(x) (x << 0)
99 #define DMC_MEMBASECONFIG_VAL(x) ( \
100 DMC_MEMBASECONFIGx_CHIP_BASE(x) | \
101 DMC_MEMBASECONFIGx_CHIP_MASK(0x780) \
104 #define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40)
105 #define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80)
107 #define DMC_PRECHCONFIG_VAL 0xFF000000
108 #define DMC_PWRDNCONFIG_VAL 0xFFFF00FF
110 #define DMC_CONCONTROL_RESET_VAL 0x0FFF0000
111 #define DFI_INIT_START (1 << 28)
112 #define EMPTY (1 << 8)
113 #define AREF_EN (1 << 5)
115 #define DFI_INIT_COMPLETE_CHO (1 << 2)
116 #define DFI_INIT_COMPLETE_CH1 (1 << 3)
118 #define RDLVL_COMPLETE_CHO (1 << 14)
119 #define RDLVL_COMPLETE_CH1 (1 << 15)
121 #define CLK_STOP_EN (1 << 0)
122 #define DPWRDN_EN (1 << 1)
123 #define DSREF_EN (1 << 5)
126 #define DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3)
127 #define DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5)
128 #define DMC_CONCONTROL_EMPTY_DISABLE (0 << 8)
129 #define DMC_CONCONTROL_EMPTY_ENABLE (1 << 8)
130 #define DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12)
131 #define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16)
132 #define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28)
135 #define CLK_DIV_CPU0_VAL ((ARM2_RATIO << 28) \
136 | (APLL_RATIO << 24) \
137 | (PCLK_DBG_RATIO << 20) \
138 | (ATB_RATIO << 16) \
139 | (PERIPH_RATIO << 12) \
141 | (CPUD_RATIO << 4) \
145 #define CLK_SRC_FSYS0_VAL 0x66666
146 #define CLK_DIV_FSYS0_VAL 0x0BB00000
149 #define HPM_RATIO 0x2
150 #define COPY_RATIO 0x0
153 #define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \
157 #define CLK_SRC_CORE0_VAL 0x00000000
160 #define CLK_SRC_CORE1_VAL 0x100
163 #define CLK_DIV_CORE0_VAL 0x00120000
166 #define CLK_DIV_CORE1_VAL 0x07070700
169 #define CLK_DIV_SYSRGT_VAL 0x00000111
172 #define CLK_DIV_ACP_VAL 0x12
175 #define CLK_DIV_SYSLFT_VAL 0x00000311
178 #define CLK_SRC_CDREX_VAL 0x1
181 #define MCLK_CDREX2_RATIO 0x0
182 #define ACLK_EFCON_RATIO 0x1
183 #define MCLK_DPHY_RATIO 0x1
184 #define MCLK_CDREX_RATIO 0x1
185 #define ACLK_C2C_200_RATIO 0x1
186 #define C2C_CLK_400_RATIO 0x1
187 #define PCLK_CDREX_RATIO 0x1
188 #define ACLK_CDREX_RATIO 0x1
190 #define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 24) \
191 | (C2C_CLK_400_RATIO << 6) \
192 | (PCLK_CDREX_RATIO << 4) \
193 | (ACLK_CDREX_RATIO))
196 #define MUX_ACLK_300_GSCL_SEL 0x0
197 #define MUX_ACLK_300_GSCL_MID_SEL 0x0
198 #define MUX_ACLK_400_G3D_MID_SEL 0x0
199 #define MUX_ACLK_333_SEL 0x0
200 #define MUX_ACLK_300_DISP1_SEL 0x0
201 #define MUX_ACLK_300_DISP1_MID_SEL 0x0
202 #define MUX_ACLK_200_SEL 0x0
203 #define MUX_ACLK_166_SEL 0x0
204 #define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \
205 | (MUX_ACLK_300_GSCL_MID_SEL << 24) \
206 | (MUX_ACLK_400_G3D_MID_SEL << 20) \
207 | (MUX_ACLK_333_SEL << 16) \
208 | (MUX_ACLK_300_DISP1_SEL << 15) \
209 | (MUX_ACLK_300_DISP1_MID_SEL << 14) \
210 | (MUX_ACLK_200_SEL << 12) \
211 | (MUX_ACLK_166_SEL << 8))
214 #define MUX_ACLK_400_G3D_SEL 0x1
215 #define MUX_ACLK_400_ISP_SEL 0x0
216 #define MUX_ACLK_400_IOP_SEL 0x0
217 #define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0
218 #define MUX_ACLK_300_GSCL_MID1_SEL 0x0
219 #define MUX_ACLK_300_DISP1_MID1_SEL 0x0
220 #define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \
221 |(MUX_ACLK_400_ISP_SEL << 24) \
222 |(MUX_ACLK_400_IOP_SEL << 20) \
223 |(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16) \
224 |(MUX_ACLK_300_GSCL_MID1_SEL << 12) \
225 |(MUX_ACLK_300_DISP1_MID1_SEL << 8))
228 #define MUX_GPLL_SEL 0x1
229 #define MUX_BPLL_USER_SEL 0x0
230 #define MUX_MPLL_USER_SEL 0x0
231 #define MUX_VPLL_SEL 0x1
232 #define MUX_EPLL_SEL 0x1
233 #define MUX_CPLL_SEL 0x1
234 #define VPLLSRC_SEL 0x0
235 #define CLK_SRC_TOP2_VAL ((MUX_GPLL_SEL << 28) \
236 | (MUX_BPLL_USER_SEL << 24) \
237 | (MUX_MPLL_USER_SEL << 20) \
238 | (MUX_VPLL_SEL << 16) \
239 | (MUX_EPLL_SEL << 12) \
240 | (MUX_CPLL_SEL << 8) \
243 #define MUX_ACLK_333_SUB_SEL 0x1
244 #define MUX_ACLK_400_SUB_SEL 0x1
245 #define MUX_ACLK_266_ISP_SUB_SEL 0x1
246 #define MUX_ACLK_266_GPS_SUB_SEL 0x0
247 #define MUX_ACLK_300_GSCL_SUB_SEL 0x1
248 #define MUX_ACLK_266_GSCL_SUB_SEL 0x1
249 #define MUX_ACLK_300_DISP1_SUB_SEL 0x1
250 #define MUX_ACLK_200_DISP1_SUB_SEL 0x1
251 #define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \
252 | (MUX_ACLK_400_SUB_SEL << 20) \
253 | (MUX_ACLK_266_ISP_SUB_SEL << 16) \
254 | (MUX_ACLK_266_GPS_SUB_SEL << 12) \
255 | (MUX_ACLK_300_GSCL_SUB_SEL << 10) \
256 | (MUX_ACLK_266_GSCL_SUB_SEL << 8) \
257 | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
258 | (MUX_ACLK_200_DISP1_SUB_SEL << 4))
261 #define ACLK_300_DISP1_RATIO 0x2
262 #define ACLK_400_G3D_RATIO 0x0
263 #define ACLK_333_RATIO 0x0
264 #define ACLK_266_RATIO 0x2
265 #define ACLK_200_RATIO 0x3
266 #define ACLK_166_RATIO 0x1
267 #define ACLK_133_RATIO 0x1
268 #define ACLK_66_RATIO 0x5
270 #define CLK_DIV_TOP0_VAL ((ACLK_300_DISP1_RATIO << 28) \
271 | (ACLK_400_G3D_RATIO << 24) \
272 | (ACLK_333_RATIO << 20) \
273 | (ACLK_266_RATIO << 16) \
274 | (ACLK_200_RATIO << 12) \
275 | (ACLK_166_RATIO << 8) \
276 | (ACLK_133_RATIO << 4) \
280 #define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3
281 #define ACLK_66_PRE_RATIO 0x1
282 #define ACLK_400_ISP_RATIO 0x1
283 #define ACLK_400_IOP_RATIO 0x1
284 #define ACLK_300_GSCL_RATIO 0x2
286 #define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \
287 | (ACLK_66_PRE_RATIO << 24) \
288 | (ACLK_400_ISP_RATIO << 20) \
289 | (ACLK_400_IOP_RATIO << 16) \
290 | (ACLK_300_GSCL_RATIO << 12))
293 #define APLL_LOCK_VAL (0x546)
295 #define MPLL_LOCK_VAL (0x546)
297 #define CPLL_LOCK_VAL (0x546)
299 #define GPLL_LOCK_VAL (0x546)
301 #define EPLL_LOCK_VAL (0x3A98)
303 #define VPLL_LOCK_VAL (0x3A98)
305 #define BPLL_LOCK_VAL (0x546)
307 #define MUX_MCLK_CDREX_SEL (1 << 4)
308 #define MUX_MCLK_DPHY_SEL (1 << 8)
310 #define MUX_APLL_SEL_MASK (1 << 0)
311 #define MUX_MPLL_FOUT_SEL (1 << 4)
312 #define MUX_BPLL_FOUT_SEL (1 << 0)
313 #define MUX_MPLL_SEL_MASK (1 << 8)
314 #define MPLL_SEL_MOUT_MPLLFOUT (2 << 8)
315 #define MUX_CPLL_SEL_MASK (1 << 8)
316 #define MUX_EPLL_SEL_MASK (1 << 12)
317 #define MUX_VPLL_SEL_MASK (1 << 16)
318 #define MUX_GPLL_SEL_MASK (1 << 28)
319 #define MUX_BPLL_SEL_MASK (1 << 0)
320 #define MUX_HPM_SEL_MASK (1 << 20)
321 #define HPM_SEL_SCLK_MPLL (1 << 21)
322 #define APLL_CON0_LOCKED (1 << 29)
323 #define MPLL_CON0_LOCKED (1 << 29)
324 #define BPLL_CON0_LOCKED (1 << 29)
325 #define CPLL_CON0_LOCKED (1 << 29)
326 #define EPLL_CON0_LOCKED (1 << 29)
327 #define GPLL_CON0_LOCKED (1 << 29)
328 #define VPLL_CON0_LOCKED (1 << 29)
329 #define CLK_REG_DISABLE 0x0
330 #define TOP2_VAL 0x0110000
339 #define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \
340 | (UART3_SEL << 12) \
350 #define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 24) \
355 #define SPI0_ISP_SEL 6
356 #define SPI1_ISP_SEL 6
357 #define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \
358 | (SPI0_ISP_SEL << 0)
361 #define SPI0_ISP_RATIO 0xf
362 #define SPI1_ISP_RATIO 0xf
363 #define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \
364 | (SPI0_ISP_RATIO << 0)
367 #define UART5_RATIO 7
368 #define UART4_RATIO 7
369 #define UART3_RATIO 7
370 #define UART2_RATIO 7
371 #define UART1_RATIO 7
372 #define UART0_RATIO 7
374 #define CLK_DIV_PERIC0_VAL ((UART3_RATIO << 12) \
375 | (UART2_RATIO << 8) \
376 | (UART1_RATIO << 4) \
379 #define SPI1_RATIO 0x7
380 #define SPI0_RATIO 0xf
381 #define SPI1_SUB_RATIO 0x0
382 #define SPI0_SUB_RATIO 0x0
383 #define CLK_DIV_PERIC1_VAL ((SPI1_SUB_RATIO << 24) \
384 | ((SPI1_RATIO << 16) \
385 | (SPI0_SUB_RATIO << 8) \
386 | (SPI0_RATIO << 0)))
389 #define SPI2_RATIO 0xf
390 #define SPI2_SUB_RATIO 0x0
391 #define CLK_DIV_PERIC2_VAL ((SPI2_SUB_RATIO << 8) \
394 #define MMC2_RATIO_MASK 0xf
395 #define MMC2_RATIO_VAL 0x3
396 #define MMC2_RATIO_OFFSET 0
398 #define MMC2_PRE_RATIO_MASK 0xff
399 #define MMC2_PRE_RATIO_VAL 0x9
400 #define MMC2_PRE_RATIO_OFFSET 8
402 #define MMC3_RATIO_MASK 0xf
403 #define MMC3_RATIO_VAL 0x1
404 #define MMC3_RATIO_OFFSET 16
406 #define MMC3_PRE_RATIO_MASK 0xff
407 #define MMC3_PRE_RATIO_VAL 0x0
408 #define MMC3_PRE_RATIO_OFFSET 24
411 #define CLK_SRC_LEX_VAL 0x0
414 #define CLK_DIV_LEX_VAL 0x10
417 #define CLK_DIV_R0X_VAL 0x10
420 #define CLK_DIV_R1X_VAL 0x10
423 #define CLK_DIV_ISP0_VAL 0x31
426 #define CLK_DIV_ISP1_VAL 0x0
429 #define CLK_DIV_ISP2_VAL 0x1
432 #define CLK_SRC_DISP1_0_VAL 0x6
438 #define CLK_DIV_DISP1_0_FIMD1 (2 << 0)
441 #define CLK_GATE_DP1_ALLOW (1 << 4)
444 #define CLK_C2C_MASK (1 << 1)
447 #define CLK_SMMUG2D_MASK (1 << 7)
448 #define CLK_SMMUSSS_MASK (1 << 6)
449 #define CLK_SMMUMDMA_MASK (1 << 5)
450 #define CLK_ID_REMAPPER_MASK (1 << 4)
451 #define CLK_G2D_MASK (1 << 3)
452 #define CLK_SSS_MASK (1 << 2)
453 #define CLK_MDMA_MASK (1 << 1)
454 #define CLK_SECJTAG_MASK (1 << 0)
457 #define CLK_EFCLK_MASK (1 << 16)
460 #define CLK_UART_ISP_MASK (1 << 31)
461 #define CLK_WDT_ISP_MASK (1 << 30)
462 #define CLK_PWM_ISP_MASK (1 << 28)
463 #define CLK_MTCADC_ISP_MASK (1 << 27)
464 #define CLK_I2C1_ISP_MASK (1 << 26)
465 #define CLK_I2C0_ISP_MASK (1 << 25)
466 #define CLK_MPWM_ISP_MASK (1 << 24)
467 #define CLK_MCUCTL_ISP_MASK (1 << 23)
468 #define CLK_INT_COMB_ISP_MASK (1 << 22)
469 #define CLK_SMMU_MCUISP_MASK (1 << 13)
470 #define CLK_SMMU_SCALERP_MASK (1 << 12)
471 #define CLK_SMMU_SCALERC_MASK (1 << 11)
472 #define CLK_SMMU_FD_MASK (1 << 10)
473 #define CLK_SMMU_DRC_MASK (1 << 9)
474 #define CLK_SMMU_ISP_MASK (1 << 8)
475 #define CLK_GICISP_MASK (1 << 7)
476 #define CLK_ARM9S_MASK (1 << 6)
477 #define CLK_MCUISP_MASK (1 << 5)
478 #define CLK_SCALERP_MASK (1 << 4)
479 #define CLK_SCALERC_MASK (1 << 3)
480 #define CLK_FD_MASK (1 << 2)
481 #define CLK_DRC_MASK (1 << 1)
482 #define CLK_ISP_MASK (1 << 0)
485 #define CLK_SPI1_ISP_MASK (1 << 13)
486 #define CLK_SPI0_ISP_MASK (1 << 12)
487 #define CLK_SMMU3DNR_MASK (1 << 7)
488 #define CLK_SMMUDIS1_MASK (1 << 6)
489 #define CLK_SMMUDIS0_MASK (1 << 5)
490 #define CLK_SMMUODC_MASK (1 << 4)
491 #define CLK_3DNR_MASK (1 << 2)
492 #define CLK_DIS_MASK (1 << 1)
493 #define CLK_ODC_MASK (1 << 0)
496 #define CLK_SMMUFIMC_LITE2_MASK (1 << 20)
497 #define CLK_SMMUFIMC_LITE1_MASK (1 << 12)
498 #define CLK_SMMUFIMC_LITE0_MASK (1 << 11)
499 #define CLK_SMMUGSCL3_MASK (1 << 10)
500 #define CLK_SMMUGSCL2_MASK (1 << 9)
501 #define CLK_SMMUGSCL1_MASK (1 << 8)
502 #define CLK_SMMUGSCL0_MASK (1 << 7)
503 #define CLK_GSCL_WRAP_B_MASK (1 << 6)
504 #define CLK_GSCL_WRAP_A_MASK (1 << 5)
505 #define CLK_CAMIF_TOP_MASK (1 << 4)
506 #define CLK_GSCL3_MASK (1 << 3)
507 #define CLK_GSCL2_MASK (1 << 2)
508 #define CLK_GSCL1_MASK (1 << 1)
509 #define CLK_GSCL0_MASK (1 << 0)
512 #define CLK_SMMUMFCR_MASK (1 << 2)
513 #define CLK_SMMUMFCL_MASK (1 << 1)
514 #define CLK_MFC_MASK (1 << 0)
516 #define SCLK_MPWM_ISP_MASK (1 << 0)
519 #define CLK_SMMUTVX_MASK (1 << 9)
520 #define CLK_ASYNCTVX_MASK (1 << 7)
521 #define CLK_HDMI_MASK (1 << 6)
522 #define CLK_MIXER_MASK (1 << 5)
523 #define CLK_DSIM1_MASK (1 << 3)
526 #define CLK_SMMUMDMA1_MASK (1 << 9)
527 #define CLK_SMMUJPEG_MASK (1 << 7)
528 #define CLK_SMMUROTATOR_MASK (1 << 6)
529 #define CLK_MDMA1_MASK (1 << 4)
530 #define CLK_JPEG_MASK (1 << 2)
531 #define CLK_ROTATOR_MASK (1 << 1)
534 #define CLK_WDT_IOP_MASK (1 << 30)
535 #define CLK_SMMUMCU_IOP_MASK (1 << 26)
536 #define CLK_SATA_PHY_I2C_MASK (1 << 25)
537 #define CLK_SATA_PHY_CTRL_MASK (1 << 24)
538 #define CLK_MCUCTL_MASK (1 << 23)
539 #define CLK_NFCON_MASK (1 << 22)
540 #define CLK_SMMURTIC_MASK (1 << 11)
541 #define CLK_RTIC_MASK (1 << 9)
542 #define CLK_MIPI_HSI_MASK (1 << 8)
543 #define CLK_USBOTG_MASK (1 << 7)
544 #define CLK_SATA_MASK (1 << 6)
545 #define CLK_PDMA1_MASK (1 << 2)
546 #define CLK_PDMA0_MASK (1 << 1)
547 #define CLK_MCU_IOP_MASK (1 << 0)
550 #define CLK_HS_I2C3_MASK (1 << 31)
551 #define CLK_HS_I2C2_MASK (1 << 30)
552 #define CLK_HS_I2C1_MASK (1 << 29)
553 #define CLK_HS_I2C0_MASK (1 << 28)
554 #define CLK_AC97_MASK (1 << 27)
555 #define CLK_SPDIF_MASK (1 << 26)
556 #define CLK_PCM2_MASK (1 << 23)
557 #define CLK_PCM1_MASK (1 << 22)
558 #define CLK_I2S2_MASK (1 << 21)
559 #define CLK_I2S1_MASK (1 << 20)
560 #define CLK_SPI2_MASK (1 << 18)
561 #define CLK_SPI0_MASK (1 << 16)
562 #define CLK_I2CHDMI_MASK (1 << 14)
563 #define CLK_I2C7_MASK (1 << 13)
564 #define CLK_I2C6_MASK (1 << 12)
565 #define CLK_I2C5_MASK (1 << 11)
566 #define CLK_I2C4_MASK (1 << 10)
567 #define CLK_I2C3_MASK (1 << 9)
568 #define CLK_I2C2_MASK (1 << 8)
569 #define CLK_I2C1_MASK (1 << 7)
570 #define CLK_I2C0_MASK (1 << 6)
573 #define CLK_RTC_MASK (1 << 20)
574 #define CLK_TZPC9_MASK (1 << 15)
575 #define CLK_TZPC8_MASK (1 << 14)
576 #define CLK_TZPC7_MASK (1 << 13)
577 #define CLK_TZPC6_MASK (1 << 12)
578 #define CLK_TZPC5_MASK (1 << 11)
579 #define CLK_TZPC4_MASK (1 << 10)
580 #define CLK_TZPC3_MASK (1 << 9)
581 #define CLK_TZPC2_MASK (1 << 8)
582 #define CLK_TZPC1_MASK (1 << 7)
583 #define CLK_TZPC0_MASK (1 << 6)
584 #define CLK_CHIPID_MASK (1 << 0)
587 #define CLK_ACP_MASK (1 << 7)
590 #define CLK_TZASC_DRBXW_MASK (1 << 23)
591 #define CLK_TZASC_DRBXR_MASK (1 << 22)
592 #define CLK_TZASC_XLBXW_MASK (1 << 21)
593 #define CLK_TZASC_XLBXR_MASK (1 << 20)
594 #define CLK_TZASC_XR1BXW_MASK (1 << 19)
595 #define CLK_TZASC_XR1BXR_MASK (1 << 18)
596 #define CLK_DPHY1_MASK (1 << 5)
597 #define CLK_DPHY0_MASK (1 << 4)
609 #define DECPROTXSET 0xFF
611 #define LPDDR3PHY_CTRL_PHY_RESET_DISABLE (1 << 0)
612 #define LPDDR3PHY_CTRL_PHY_RESET_ENABLE (0 << 0 )
614 #define PHY_CON0_RESET_VAL 0x17020a40
615 #define P0_CMD_EN (1 << 14)
616 #define BYTE_RDLVL_EN (1 << 13)
617 #define CTRL_SHGATE (1 << 8)
619 #define PHY_CON1_RESET_VAL 0x09210100
620 #define CTRL_GATEDURADJ_MASK (0xf << 20)
622 #define PHY_CON2_RESET_VAL 0x00010004
623 #define INIT_DESKEW_EN (1 << 6)
624 #define RDLVL_GATE_EN (1 << 24)
627 #define PHY_CON16_RESET_VAL 0x08000304
629 #define ZQ_CLK_DIV_EN (1 << 18)
630 #define ZQ_MANUAL_STR (1 << 1)
631 #define ZQ_DONE (1 << 0)
633 #define CTRL_RDLVL_GATE_ENABLE 1
634 #define CTRL_RDLVL_GATE_DISABLE 1
637 #define DIRECT_CMD_NOP 0x07000000
638 #define DIRECT_CMD_PALL 0x01000000
639 #define DIRECT_CMD_ZQINIT 0x0a000000
640 #define DIRECT_CMD_CHANNEL_SHIFT 28
641 #define DIRECT_CMD_CHIP_SHIFT 20
644 #define PHY_CONTROL0_RESET_VAL 0x0
645 #define MEM_TERM_EN (1 << 31)
646 #define PHY_TERM_EN (1 << 30)
647 #define DMC_CTRL_SHGATE (1 << 29)
648 #define FP_RSYNC (1 << 3)
651 #define IMP_OUTPUT_DRV_40_OHM 0x5
652 #define IMP_OUTPUT_DRV_30_OHM 0x7
653 #define CA_CK_DRVR_DS_OFFSET 9
654 #define CA_CKE_DRVR_DS_OFFSET 6
655 #define CA_CS_DRVR_DS_OFFSET 3
656 #define CA_ADR_DRVR_DS_OFFSET 0
658 #define PHY_CON42_CTRL_BSTLEN_SHIFT 8
659 #define PHY_CON42_CTRL_RDLAT_SHIFT 0
void update_reset_dll(struct exynos5_dmc *, enum ddr_mode)
int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, int mem_reset)
void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc)
int dmc_config_zq(struct mem_timings *mem, struct exynos5_phy_control *phy0_ctrl, struct exynos5_phy_control *phy1_ctrl)
void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc)
@ SETUP_ERR_RDLV_COMPLETE_TIMEOUT
@ SETUP_ERR_ZQ_CALIBRATION_FAILURE
void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc)