coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.c
Go to the documentation of this file.
1
/* SPDX-License-Identifier: GPL-2.0-only */
2
3
#include <baseboard/gpio.h>
4
#include <baseboard/variants.h>
5
#include <
commonlib/helpers.h
>
6
7
/* Pad configuration in ramstage */
8
static
const
struct
pad_config
override_gpio_table
[] = {
9
/* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */
10
PAD_CFG_GPO
(
GPP_A7
, 1, DEEP),
11
/* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */
12
PAD_CFG_GPO
(
GPP_A8
, 0, DEEP),
13
/* A10 : I2S2_RXD ==> EN_SPKR_PA */
14
PAD_CFG_GPO
(
GPP_A10
, 1, DEEP),
15
/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
16
PAD_CFG_GPO
(
GPP_A13
, 1, DEEP),
17
/* A15 : USB_OC2# ==> NC */
18
PAD_NC
(
GPP_A15
,
NONE
),
19
/* A16 : USB_OC3# ==> USB_C0_OC_ODL */
20
PAD_CFG_NF
(
GPP_A16
,
NONE
, DEEP, NF1),
21
/* A22 : DDPC_CTRLDATA ==> EN_PP3300_SSD */
22
PAD_CFG_GPO
(
GPP_A22
, 1, DEEP),
23
/* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */
24
PAD_CFG_NF
(
GPP_A23
,
NONE
, DEEP, NF1),
25
26
/* B2 : VRALERT# ==> NOT USED */
27
PAD_NC
(
GPP_B2
,
NONE
),
28
/* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */
29
PAD_CFG_NF
(
GPP_B9
,
NONE
, DEEP, NF1),
30
/* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */
31
PAD_CFG_NF
(
GPP_B10
,
NONE
, DEEP, NF1),
32
/* B22 : GSPI1_MOSI ==> NOT USED */
33
PAD_NC
(
GPP_B22
,
NONE
),
34
35
/* C10 : UART0_RTS# ==> USI_RST_L */
36
PAD_CFG_GPO
(
GPP_C10
, 0, DEEP),
37
/* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */
38
PAD_CFG_NF
(
GPP_C16
,
NONE
, DEEP, NF1),
39
/* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */
40
PAD_CFG_NF
(
GPP_C17
,
NONE
, DEEP, NF1),
41
/* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */
42
PAD_CFG_NF
(
GPP_C18
,
NONE
, DEEP, NF1),
43
/* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */
44
PAD_CFG_NF
(
GPP_C19
,
NONE
, DEEP, NF1),
45
46
/* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */
47
PAD_CFG_NF
(
GPP_D6
,
NONE
, DEEP, NF1),
48
/* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
49
PAD_CFG_NF
(
GPP_D8
,
NONE
, DEEP, NF1),
50
/* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
51
PAD_CFG_GPO
(
GPP_D16
, 1, DEEP),
52
/* D17 : ISH_GP4 ==> EN_CVF_PWR */
53
PAD_CFG_GPO
(
GPP_D17
, 1, DEEP),
54
55
/* E0 : SATAXPCIE0 ==> NC */
56
PAD_NC
(
GPP_E0
,
NONE
),
57
/* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */
58
PAD_CFG_GPI
(
GPP_E2
,
NONE
, DEEP),
59
/* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */
60
PAD_CFG_GPI
(
GPP_E4
,
NONE
, DEEP),
61
/* E7 : CPU_GP1 ==> USI_INT */
62
PAD_CFG_GPI_APIC
(
GPP_E7
,
NONE
, PLTRST, LEVEL,
NONE
),
63
/* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */
64
PAD_CFG_GPI
(
GPP_E11
,
NONE
, DEEP),
65
/* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */
66
PAD_CFG_GPI_IRQ_WAKE(
GPP_E15
,
NONE
, DEEP, LEVEL, INVERT),
67
/* E18 : DDP1_CTRLCLK ==> NC */
68
PAD_NC
(
GPP_E18
,
NONE
),
69
/* E19 : DDP1_CTRLCLK ==> NC */
70
PAD_NC
(
GPP_E19
,
NONE
),
71
/* E20 : DDP2_CTRLCLK ==> NC */
72
PAD_NC
(
GPP_E20
,
NONE
),
73
/* E21 : DDP1_CTRLCLK ==> NC */
74
PAD_NC
(
GPP_E21
,
NONE
),
75
76
/* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */
77
PAD_CFG_GPI_INT
(
GPP_F8
,
NONE
, PLTRST, EDGE_BOTH),
78
/* F11 : THC1_SPI2_CLK ==> NC */
79
PAD_NC
(
GPP_F11
,
NONE
),
80
/* F13 : GSXDOUT ==> WiFi_DISABLE_L */
81
PAD_CFG_GPO
(
GPP_F13
, 1, DEEP),
82
/* F19 : SRCCLKREQ6# ==> WLAN_INT_L */
83
PAD_CFG_GPI_SCI_LOW
(
GPP_F19
,
NONE
, DEEP, EDGE_SINGLE),
84
/* F20 : EXT_PWR_GATE# ==> NC */
85
PAD_NC
(
GPP_F20
,
NONE
),
86
/* F21 : EXT_PWR_GATE2# ==> NC */
87
PAD_NC
(
GPP_F21
,
NONE
),
88
/* F22 : VNN_CTRL ==> NC */
89
PAD_NC
(
GPP_F22
,
NONE
),
90
91
/* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */
92
PAD_CFG_GPO
(
GPP_H3
, 1, DEEP),
93
/* H4 : I2C2_SDA ==> NC */
94
PAD_NC
(
GPP_H4
,
NONE
),
95
/* H5 : I2C2_SCL ==> NC */
96
PAD_NC
(
GPP_H5
,
NONE
),
97
/* H10 : SRCCLKREQ4# ==> NC */
98
PAD_NC
(
GPP_H10
,
NONE
),
99
/* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */
100
PAD_CFG_GPO
(
GPP_H11
, 1, DEEP),
101
/* H12 : M2_SKT2_CFG0 ==> SPKR_INT_R */
102
PAD_CFG_GPI
(
GPP_H12
,
NONE
, DEEP),
103
/* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */
104
PAD_CFG_GPI
(
GPP_H13
,
NONE
, DEEP),
105
106
/* R0 : HDA_BCLK ==> I2S0_HP_SCLK */
107
PAD_CFG_NF
(
GPP_R0
,
NONE
, DEEP, NF2),
108
/* R1 : HDA_SYNC ==> I2S0_HP_SFRM */
109
PAD_CFG_NF
(
GPP_R1
,
NONE
, DEEP, NF2),
110
/* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */
111
PAD_CFG_NF
(
GPP_R2
, DN_20K, DEEP, NF2),
112
/* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */
113
PAD_CFG_NF
(
GPP_R3
,
NONE
, DEEP, NF2),
114
/* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */
115
PAD_CFG_NF
(
GPP_R5
,
NONE
, DEEP, NF2),
116
/* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */
117
PAD_CFG_NF
(
GPP_R6
,
NONE
, DEEP, NF2),
118
/* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */
119
PAD_CFG_NF
(
GPP_R7
,
NONE
, DEEP, NF2),
120
121
/* S6 : SNDW3_CLK ==> DMIC_CLK0 */
122
PAD_CFG_NF
(
GPP_S6
,
NONE
, DEEP, NF2),
123
/* S7 : SNDW3_DATA ==> DMIC_DATA0 */
124
PAD_CFG_NF
(
GPP_S7
,
NONE
, DEEP, NF2),
125
126
/* GPD9: SLP_WLAN# ==> SLP_WLAN_L_CAP_SITE */
127
PAD_CFG_NF
(
GPD9
,
NONE
, DEEP, NF1),
128
};
129
130
/* Early pad configuration in bootblock */
131
static
const
struct
pad_config
early_gpio_table
[] = {
132
/* C8 : UART0 RX */
133
PAD_CFG_NF
(
GPP_C8
,
NONE
, DEEP, NF1),
134
/* C9 : UART0 TX */
135
PAD_CFG_NF
(
GPP_C9
,
NONE
, DEEP, NF1),
136
137
/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
138
PAD_CFG_NF
(
GPP_A12
,
NONE
, DEEP, NF1),
139
/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
140
/* assert reset on reboot */
141
PAD_CFG_GPO
(
GPP_A13
, 0, DEEP),
142
/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
143
PAD_CFG_GPI
(
GPP_A17
,
NONE
, DEEP),
144
/* A22 : DDPC_CTRLDATA ==> EN_PP3300_SSD */
145
PAD_CFG_GPO
(
GPP_A22
, 1, DEEP),
146
147
/* B11 : PMCALERT# ==> PCH_WP_OD */
148
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_B11
,
NONE
, DEEP),
149
/* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
150
PAD_CFG_NF
(
GPP_B15
,
NONE
, DEEP, NF1),
151
/* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */
152
PAD_CFG_NF
(
GPP_B16
,
NONE
, DEEP, NF1),
153
/* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */
154
PAD_CFG_NF
(
GPP_B17
,
NONE
, DEEP, NF1),
155
/* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
156
PAD_CFG_NF
(
GPP_B18
,
NONE
, DEEP, NF1),
157
158
/* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
159
PAD_CFG_GPI_APIC
(
GPP_C21
,
NONE
, PLTRST, LEVEL, INVERT),
160
161
/* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
162
PAD_CFG_GPO
(
GPP_D16
, 1, DEEP),
163
164
/* E15 : ISH_GP6 ==> NC */
165
PAD_NC
(
GPP_E15
,
NONE
),
166
167
/* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */
168
PAD_CFG_GPO
(
GPP_H11
, 1, DEEP),
169
};
170
171
const
struct
pad_config
*
variant_override_gpio_table
(
size_t
*num)
172
{
173
*num =
ARRAY_SIZE
(
override_gpio_table
);
174
return
override_gpio_table
;
175
}
176
177
const
struct
pad_config
*
variant_early_gpio_table
(
size_t
*num)
178
{
179
*num =
ARRAY_SIZE
(
early_gpio_table
);
180
return
early_gpio_table
;
181
}
GPD9
#define GPD9
Definition:
gpio_soc_defs.h:390
GPP_D8
#define GPP_D8
Definition:
gpio_soc_defs.h:260
GPP_D17
#define GPP_D17
Definition:
gpio_soc_defs.h:269
GPP_F21
#define GPP_F21
Definition:
gpio_soc_defs.h:594
GPP_E0
#define GPP_E0
Definition:
gpio_soc_defs.h:628
GPP_R7
#define GPP_R7
Definition:
gpio_soc_defs.h:676
GPP_F20
#define GPP_F20
Definition:
gpio_soc_defs.h:593
GPP_H11
#define GPP_H11
Definition:
gpio_soc_defs.h:227
GPP_B16
#define GPP_B16
Definition:
gpio_soc_defs.h:69
GPP_B2
#define GPP_B2
Definition:
gpio_soc_defs.h:55
GPP_R3
#define GPP_R3
Definition:
gpio_soc_defs.h:672
GPP_D6
#define GPP_D6
Definition:
gpio_soc_defs.h:258
GPP_H12
#define GPP_H12
Definition:
gpio_soc_defs.h:228
GPP_C9
#define GPP_C9
Definition:
gpio_soc_defs.h:546
GPP_R6
#define GPP_R6
Definition:
gpio_soc_defs.h:675
GPP_R0
#define GPP_R0
Definition:
gpio_soc_defs.h:669
GPP_B15
#define GPP_B15
Definition:
gpio_soc_defs.h:68
GPP_H13
#define GPP_H13
Definition:
gpio_soc_defs.h:229
GPP_C8
#define GPP_C8
Definition:
gpio_soc_defs.h:545
GPP_S7
#define GPP_S7
Definition:
gpio_soc_defs.h:167
GPP_B22
#define GPP_B22
Definition:
gpio_soc_defs.h:75
GPP_A23
#define GPP_A23
Definition:
gpio_soc_defs.h:142
GPP_C18
#define GPP_C18
Definition:
gpio_soc_defs.h:555
GPP_C17
#define GPP_C17
Definition:
gpio_soc_defs.h:554
GPP_A7
#define GPP_A7
Definition:
gpio_soc_defs.h:126
GPP_A16
#define GPP_A16
Definition:
gpio_soc_defs.h:135
GPP_A12
#define GPP_A12
Definition:
gpio_soc_defs.h:131
GPP_C10
#define GPP_C10
Definition:
gpio_soc_defs.h:547
GPP_E7
#define GPP_E7
Definition:
gpio_soc_defs.h:635
GPP_C16
#define GPP_C16
Definition:
gpio_soc_defs.h:553
GPP_F13
#define GPP_F13
Definition:
gpio_soc_defs.h:586
GPP_S6
#define GPP_S6
Definition:
gpio_soc_defs.h:166
GPP_E2
#define GPP_E2
Definition:
gpio_soc_defs.h:630
GPP_E19
#define GPP_E19
Definition:
gpio_soc_defs.h:647
GPP_H5
#define GPP_H5
Definition:
gpio_soc_defs.h:221
GPP_C21
#define GPP_C21
Definition:
gpio_soc_defs.h:558
GPP_R2
#define GPP_R2
Definition:
gpio_soc_defs.h:671
GPP_B9
#define GPP_B9
Definition:
gpio_soc_defs.h:62
GPP_E18
#define GPP_E18
Definition:
gpio_soc_defs.h:646
GPP_H3
#define GPP_H3
Definition:
gpio_soc_defs.h:219
GPP_A10
#define GPP_A10
Definition:
gpio_soc_defs.h:129
GPP_A8
#define GPP_A8
Definition:
gpio_soc_defs.h:127
GPP_B11
#define GPP_B11
Definition:
gpio_soc_defs.h:64
GPP_B18
#define GPP_B18
Definition:
gpio_soc_defs.h:71
GPP_R5
#define GPP_R5
Definition:
gpio_soc_defs.h:674
GPP_E20
#define GPP_E20
Definition:
gpio_soc_defs.h:648
GPP_A15
#define GPP_A15
Definition:
gpio_soc_defs.h:134
GPP_F8
#define GPP_F8
Definition:
gpio_soc_defs.h:581
GPP_C19
#define GPP_C19
Definition:
gpio_soc_defs.h:556
GPP_A13
#define GPP_A13
Definition:
gpio_soc_defs.h:132
GPP_E15
#define GPP_E15
Definition:
gpio_soc_defs.h:643
GPP_B10
#define GPP_B10
Definition:
gpio_soc_defs.h:63
GPP_E11
#define GPP_E11
Definition:
gpio_soc_defs.h:639
GPP_A22
#define GPP_A22
Definition:
gpio_soc_defs.h:141
GPP_F22
#define GPP_F22
Definition:
gpio_soc_defs.h:595
GPP_F11
#define GPP_F11
Definition:
gpio_soc_defs.h:584
GPP_D16
#define GPP_D16
Definition:
gpio_soc_defs.h:268
GPP_H10
#define GPP_H10
Definition:
gpio_soc_defs.h:226
GPP_E21
#define GPP_E21
Definition:
gpio_soc_defs.h:649
GPP_A17
#define GPP_A17
Definition:
gpio_soc_defs.h:136
GPP_B17
#define GPP_B17
Definition:
gpio_soc_defs.h:70
GPP_E4
#define GPP_E4
Definition:
gpio_soc_defs.h:632
GPP_F19
#define GPP_F19
Definition:
gpio_soc_defs.h:592
GPP_H4
#define GPP_H4
Definition:
gpio_soc_defs.h:220
GPP_R1
#define GPP_R1
Definition:
gpio_soc_defs.h:670
ARRAY_SIZE
#define ARRAY_SIZE(a)
Definition:
helpers.h:12
helpers.h
variant_early_gpio_table
const struct pad_config * variant_early_gpio_table(size_t *num)
Definition:
gpio.c:204
variant_override_gpio_table
const struct pad_config *__weak variant_override_gpio_table(size_t *num)
Definition:
gpio.c:450
override_gpio_table
static const struct pad_config override_gpio_table[]
Definition:
gpio.c:8
early_gpio_table
static const struct pad_config early_gpio_table[]
Definition:
gpio.c:131
NONE
@ NONE
Definition:
qup_se_handlers_common.h:196
PAD_NC
#define PAD_NC(pin)
Definition:
gpio_defs.h:263
PAD_CFG_GPI
#define PAD_CFG_GPI(pad, pull, rst)
Definition:
gpio_defs.h:284
PAD_CFG_GPI_SCI_LOW
#define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig)
Definition:
gpio_defs.h:452
PAD_CFG_NF
#define PAD_CFG_NF(pad, pull, rst, func)
Definition:
gpio_defs.h:197
PAD_CFG_GPI_INT
#define PAD_CFG_GPI_INT(pad, pull, rst, trig)
Definition:
gpio_defs.h:348
PAD_CFG_GPI_APIC
#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv)
Definition:
gpio_defs.h:376
PAD_CFG_GPO
#define PAD_CFG_GPO(pad, val, rst)
Definition:
gpio_defs.h:247
PAD_CFG_GPI_GPIO_DRIVER
#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst)
Definition:
gpio_defs.h:323
pad_config
Definition:
gpio.h:75
src
mainboard
google
volteer
variants
lindar
gpio.c
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